half_adder.v

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

module half_adder(sum,c_out,a,b);
output sum,c_out;
input a,b;
xor(sum,a,b);
and(c_out,a,b);
endmodule

module half_adder_test;
reg a,b;
wire sum,c_out;
half_adder A1(sum,c_out,a,b);
initial
  begin
    a=0;b=0;
    #10 a=1;b=1;
    #10 a=1;b=0;
    #10 a=0;b=0;
    #10 a=0;b=1;
    #10 a=1;b=1;
    #10 a=0;b=0;
    #10 a=1;b=0;
    #10 a=1;b=1;
    #10 a=0;b=1;
  end
endmodule