shift_register_3.v

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

module shift_register_3(d_out,reg_a,reg_b,d_in,clk);
output d_out,reg_a,reg_b;
input d_in,clk;
reg d_out,reg_a,reg_b;
always@(posedge clk)
  begin
    d_out=reg_b;
    reg_b=reg_a;
    reg_a=d_in;
  end
endmodule