clk_counter_test.v.bak

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

module clk_counter_test;
wire count_out;
reg clk;
clk_counter M1(count_out,clk);
initial
  begin
    clk=0;
    #10 clk=1;
    #10 clk=0;
    #10 clk=1;
    #10 clk=0;
    #10 clk=1;
    #10 clk=0;
    #10 clk=1;
    #10 clk=0;
    #10 clk=1;
  end
endmodule