traffic_lights.v.bak

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

module traffic_lights(red,amber,green);
output red,amber,green;
reg[2:1] order;
reg clock,red,amber,green;
parameter on=1,off=0,red_tics=350,amber_tics=30,green_tics=200;
initial
  begin
    order=2'b00;
    light(red,amber,green,0,order);
  end
always
  begin
    order=2'b01;
    light(red,amber,green,red_tics,order);
    order=2'b10;
    light(red,amber,green,green_tics,order);
    order=2'b11;
    light(red,amber,grenn,amber_tics,order);
  end
task light;
output red;
output amber;
output green;
input[31:0] tic_time;
input[2:1] order;
begin
  red=off;
  green=off;
  amber=off;
  case(order)
      2'b01     :      red=on;
      2'b10     :      green=on;
      2'b11     :      amber=on;
  endcase
  repeat(tic_time)@(posedge clock);
  red=off;
  green=off;
  amber=off;
end
endtask
always
  begin
    #100 clock=0;
    #100 clock=1;
  end
endmodule