level_and_edge_sensitive_compare.v

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

module level_edge_sensitive_compare(flag1,flag2);
output flag1,flag2;
reg enable,flag1,flag2;
initial
  begin
    flag1=1;
    flag2=1;
    enable=1;
    #20 enable=0;
    #10 enable=1;
    #10 $stop;
  end
initial
  begin
    #10;
    wait(enable==1) flag1=~flag1;
  end
initial
  begin
    #10;
    @(posedge enable) 
      flag2=~flag2;
  end
endmodule