ex3.v.bak

该代码中有不少关于学习verilog HDL的例子,对初学者有帮助

module ex3;
integer a,b;
parameter size=7;
initial
  begin
    a=2;
    b=1;
    repeat(size) begin
      #5 a<=a+1;
      #5 b<=b+1;
    end
  end
initial
  $monitor($time,"a=%d,b=%d",a,b);
endmodule