__projnav.log

来自「ISE7.1」· LOG 代码 · 共 1,605 行 · 第 1/5 页

Compiling vhdl file "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" in Library work.
Entity <narrow_wide_pulse_generate> compiled.
ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 69. parse error, unexpected ROW
ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 78. parse error, unexpected WHEN, expecting END
ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 83. parse error, unexpected ELSE, expecting END
ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 86. parse error, unexpected IF, expecting PROCESS
ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 92. parse error, unexpected ELSE, expecting END
ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 95. parse error, unexpected IF, expecting PROCESS
--> 

Total memory usage is 77152 kilobytes

Number of errors   :    6 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------







Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" in Library work.
ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 69. parse error, unexpected ROW
ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 78. parse error, unexpected WHEN, expecting END
ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 83. parse error, unexpected ELSE, expecting END
ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 86. parse error, unexpected IF, expecting PROCESS
ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 92. parse error, unexpected ELSE, expecting END
ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 95. parse error, unexpected IF, expecting PROCESS
--> 

Total memory usage is 77152 kilobytes

Number of errors   :    6 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)

ERROR: XST failed
Process "Synthesize" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------










Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" in Library work.
Entity <narrow_wide_pulse_generate> compiled.
Entity <narrow_wide_pulse_generate> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <narrow_wide_pulse_generate> (Architecture <behavioral>).
Entity <narrow_wide_pulse_generate> analyzed. Unit <narrow_wide_pulse_generate> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <narrow_wide_pulse_generate>.
    Related source file is "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | log                                            |
    | Power Up State     | log                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <narrow_wide_pulse>.
    Found 32-bit comparator greatequal for signal <$n0004> created at line 70.
    Found 32-bit comparator greater for signal <$n0005> created at line 79.
    Found 32-bit comparator greater for signal <$n0006> created at line 88.
    Found 32-bit adder for signal <$n0012> created at line 68.
    Found 32-bit register for signal <cnt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  33 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   3 Comparator(s).
Unit <narrow_wide_pulse_generate> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <FSM_0> on signal <state[1:2]> with sequential encoding.
--------------------
 State  | Encoding
--------------------
 log    | 00
 narrow | 01
 wide   | 10
--------------------
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 1
# Adders/Subtractors               : 1
 32-bit adder                      : 1
# Registers                        : 4
 1-bit register                    : 3
 32-bit register                   : 1
# Comparators                      : 3
 32-bit comparator greatequal      : 1
 32-bit comparator greater         : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <narrow_wide_pulse_generate> ...
Loading device for application Rf_Device from file '2v500.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block narrow_wide_pulse_generate, actual ratio is 2.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v500fg456-4 

 Number of Slices:                      58  out of   3072     1%  
 Number of Slice Flip Flops:            35  out of   6144     0%  
 Number of 4 input LUTs:               106  out of   6144     1%  
 Number of bonded IOBs:                  3  out of    264     1%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 35    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.264ns (Maximum Frequency: 137.675MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 5.630ns
   Maximum combinational path delay: No path found

=========================================================================


Project Navigator Auto-Make Log File
-------------------------------------





Project Navigator Auto-Make Log File
-------------------------------------








Project Navigator Auto-Make Log File
-------------------------------------





Project Navigator Auto-Make Log File
-------------------------------------



Reading D:/tcl/vsim/pref.tcl 

# 6.1e

# do wide_narrow_pulse.ado 
listening on address 127.0.0.1 port 1200
# ** Warning: (vlib-34) Library already exists at "work".
# resume
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Compiling entity narrow_wide_pulse_generate
# -- Compiling architecture behavioral of narrow_wide_pulse_generate
# Model Technology ModelSim SE vcom 6.1e Compiler 2006.03 Mar  8 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Loading package std_logic_unsigned
# -- Loading package textio
# -- Loading package std_logic_textio
# -- Compiling entity wide_narrow_pulse
# -- Compiling architecture testbench_arch of wide_narrow_pulse
# vsim -lib work -t 1ps wide_narrow_pulse 
# //  ModelSim SE 6.1e Mar  8 2006 
# //
# //  Copyright 2006 Mentor Graphics Corporation
# //              All Rights Reserved.
# //
# //  THIS WORK CONTAINS TRADE SECRET AND 
# //  PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# //  OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# //  AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading d:\win32/../std.standard
# Loading d:\win32/../ieee.std_logic_1164(body)
# Loading d:\win32/../ieee.std_logic_arith(body)
# Loading d:\win32/../ieee.std_logic_unsigned(body)
# Loading d:\win32/../std.textio(body)
# Loading d:\win32/../ieee.std_logic_textio(body)
# Loading work.wide_narrow_pulse(testbench_arch)
# ** Warning: (vsim-3479) Time unit 'fs' is less than the simulator resolution (1ps).
#    Time: 0 ps  Iteration: 0  Region: /
# Loading work.narrow_wide_pulse_generate(behavioral)
# ** Failure: Success! Simulation for annotation completed
#    Time: 1000100 ns  Iteration: 0  Process: /wide_narrow_pulse/line__105 File: wide_narrow_pulse.ant
# Break at wide_narrow_pulse.ant line 115
# Stopped at wide_narrow_pulse.ant line 115 


Project Navigator Auto-Make Log File
-------------------------------------





Project Navigator Auto-Make Log File
-------------------------------------








Project Navigator Auto-Make Log File
-------------------------------------





Project Navigator Auto-Make Log File
-------------------------------------








Project Navigator Auto-Make Log File
-------------------------------------