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WARNING:Xst:1291 - FF/Latch <acumulator_wide/Q_1> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_wide/Q_2> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_wide/Q_3> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_wide/Q_4> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_wide/Q_5> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_log/Q_0> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_log/Q_1> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_log/Q_2> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_log/Q_3> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_log/Q_4> is unconnected in block <top_fmdm_project>.
WARNING:Xst:1291 - FF/Latch <acumulator_log/Q_5> is unconnected in block <top_fmdm_project>.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block top_fmdm_project, actual ratio is 14.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v500fg456-4 

 Number of Slices:                     443  out of   3072    14%  
 Number of Slice Flip Flops:           508  out of   6144     8%  
 Number of 4 input LUTs:               728  out of   6144    11%  
 Number of bonded IOBs:                 74  out of    264    28%  
 Number of BRAMs:                        1  out of     32     3%  
 Number of GCLKs:                        3  out of     16    18%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-------------------------------------------------+----------------------------------+-------+
Clock Signal                                     | Clock buffer(FF name)            | Load  |
-------------------------------------------------+----------------------------------+-------+
uart/u_baud/baud_bclk:Q                          | BUFG                             | 149   |
selected_clk(clk_select/selected_delay_clk1500:O)| BUFG(*)(data_adjust_wide/data2_4)| 318   |
fifo/GND:G                                       | NONE                             | 2     |
data_adjust_log/mux_en:Q                         | NONE                             | 8     |
clk20mhz                                         | BUFGP                            | 33    |
-------------------------------------------------+----------------------------------+-------+
(*) This 1 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.229ns (Maximum Frequency: 138.332MHz)
   Minimum input arrival time before clock: 4.854ns
   Maximum output required time after clock: 13.559ns
   Maximum combinational path delay: 13.348ns

=========================================================================




Started process "Translate".

ChipScope: inserterlauncher -mode insert -ise_project_dir f:\vhdlproject\vhdl0716 -proj adc_test.cdc -intstyle ise -dd f:\vhdlproject\vhdl0716/_ngo -uc top_fmdm_project.ucf -p xc2v500-fg456-4 top_fmdm_project.ngc top_fmdm_project_cs.ngc 
ChipScope: Started ChipScope Core Insertion Operation
ChipScope: inserterlauncher -mode insert -ise_project_dir f:\vhdlproject\vhdl0716 -proj adc_test.cdc -intstyle ise -dd f:\vhdlproject\vhdl0716/_ngo -uc top_fmdm_project.ucf -p xc2v500-fg456-4 top_fmdm_project.ngc top_fmdm_project_cs.ngc 
ChipScope: ngcbuild -dd f:\vhdlproject\vhdl0716/_ngo -p xc2v500-fg456-4 -i f:\vhdlproject\vhdl0716\top_fmdm_project.ngc f:\vhdlproject\vhdl0716\top_fmdm_project_cs.ngc
ChipScope: ChipScope Software Version: 7.1.03i     Build 07103.5.161.2     Registration ID: 9619118553733098
ChipScope: ISE Software Version: 7.1.04i     Registration ID: 9009397784384039
ChipScope: Loading CDC project f:\vhdlproject\vhdl0716\adc_test.cdc
ChipScope: Core Generation and Insertion Operations Complete.
ChipScope: Please Ignore NgdBuild:454 icon_control* warnings - these are normal for ChipScope Core Insertions.

Command Line: ngdbuild -intstyle ise -dd f:\vhdlproject\vhdl0716/_ngo -nt
timestamp -uc top_fmdm_project.ucf -p xc2v500-fg456-4 top_fmdm_project_cs.ngc
top_fmdm_project.ngd 

Reading NGO file 'F:/vhdlproject/vhdl0716/top_fmdm_project_cs.ngc' ...

Applying constraints in "top_fmdm_project.ucf" to the design...

Checking timing specifications ...
Checking expanded design ...
WARNING:NgdBuild:440 - FF primitive 'fifo/BU124' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive 'fifo/BU279' has unconnected output pin
WARNING:NgdBuild:452 - logical net 'fifo/ainit' has no driver

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   3

Writing NGD file "top_fmdm_project.ngd" ...

Writing NGDBUILD log file "top_fmdm_project.bld"...

NGDBUILD done.




Started process "Map".

Using target part "2v500fg456-4".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    2
Logic Utilization:
  Total Number Slice Registers:       829 out of   6,144   13%
    Number used as Flip Flops:                   821
    Number used as Latches:                        8
  Number of 4 input LUTs:             696 out of   6,144   11%
Logic Distribution:
  Number of occupied Slices:          771 out of   3,072   25%
  Number of Slices containing only related logic:     771 out of     771  100%
  Number of Slices containing unrelated logic:          0 out of     771    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          1,088 out of   6,144   17%
  Number used as logic:               696
  Number used as a route-thru:        245
  Number used as Shift registers:     147

  Number of bonded IOBs:               74 out of     264   28%
    IOB Flip Flops:                    56
  Number of Block RAMs:                21 out of      32   65%
  Number of GCLKs:                      4 out of      16   25%
  Number of BSCANs:                     1 out of       1  100%

   Number of RPM macros:           12
Total equivalent gate count for design:  1,399,089
Additional JTAG gate count for IOBs:  3,552
Peak Memory Usage:  127 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "top_fmdm_project_map.mrp" for details.




Started process "Place & Route".




Constraints file: top_fmdm_project.pcf.
Loading device for application Rf_Device from file '2v500.nph' in environment
D:/Xilinx.
   "top_fmdm_project" is an NCD, version 3.1, device xc2v500, package fg456,
speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000
Celsius)
Initializing voltage to 1.425 Volts. (default - Range: 1.425 to 1.575 Volts)

WARNING:Timing:2666 - Constraint ignored: PATH "TS_U_TO_D_path" TIG;

Device speed data version:  "PRODUCTION 1.121 2005-07-22".


Device Utilization Summary:

   Number of BSCANs                    1 out of 1     100%
   Number of BUFGMUXs                  4 out of 16     25%
   Number of External IOBs            74 out of 264    28%
      Number of LOCed IOBs            74 out of 74    100%

   Number of RAMB16s                  21 out of 32     65%
   Number of SLICEs                  771 out of 3072   25%


Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98d433) REAL time: 5 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 5 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 5 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 5 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 5 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 5 secs 

Phase 7.8
.............
..
Phase 7.8 (Checksum:ad36d9) REAL time: 12 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 12 secs 

Phase 9.18
Phase 9.18 (Checksum:55d4a77) REAL time: 13 secs 

Phase 10.5
Phase 10.5 (Checksum:5f5e0f6) REAL time: 13 secs 

Phase 11.27
Phase 11.27 (Checksum:68e7775) REAL time: 13 secs 

Phase 12.24
Phase 12.24 (Checksum:7270df4) REAL time: 13 secs 

Writing design to file top_fmdm_project.ncd


Total REAL time to Placer completion: 14 secs 
Total CPU time to Placer completion: 13 secs 

Starting Router

Phase 1: 6263 unrouted;       REAL time: 17 secs 

Phase 2: 5188 unrouted;       REAL time: 17 secs 

Phase 3: 959 unrouted;       REAL time: 18 secs 

Phase 4: 959 unrouted; (0)      REAL time: 18 secs 

Phase 5: 959 unrouted; (0)      REAL time: 18 secs 

Phase 6: 959 unrouted; (0)      REAL time: 18 secs 

Phase 7: 0 unrouted; (0)      REAL time: 19 secs 

Phase 8: 0 unrouted; (0)      REAL time: 21 secs 

WARNING:Route - CLK Net:adc1_clk_OBUF
may have excessive skew because 2 NON-CLK pins
failed to route using a CLK template.
WARNING:Route - CLK Net:data_adjust_log/mux_en
may have excessive skew because 4 NON-CLK pins
failed to route using a CLK template.

Total REAL time to Router completion: 21 secs 
Total CPU time to Router completion: 19 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|    icon_control0<0> |     BUFGMUX7P| No   |  105 |  0.239     |  1.029      |
+---------------------+--------------+------+------+------------+-------------+
|       adc1_clk_OBUF |     BUFGMUX4S| No   |  402 |  0.232     |  1.022      |
+---------------------+--------------+------+------+------------+-------------+
|      clk20mhz_BUFGP |     BUFGMUX2S| No   |   17 |  0.007     |  0.972      |
+---------------------+--------------+------+------+------------+-------------+
|uart/u_baud/baud_bcl |              |      |      |            |             |
|                   k |     BUFGMUX1P| No   |   89 |  0.183     |  1.031      |
+---------------------+--------------+------+------+------------+-------------+
|U_icon_pro/iupdate_o |              |      |      |            |             |
|                  ut |         Local|      |    1 |  0.000     |  1.503      |
+---------------------+--------------+------+------+------------+-------------+
|data_adjust_log/mux_ |              |      |      |            |             |
|                  en |         Local|      |   12 |  0.016     |  1.622      |
+---------------------+--------------+------+------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  TS_J_TO_J = MAXDELAY FROM TIMEGRP "J_CLK" | 30.000ns   | 10.578ns   | 7    
   TO TIMEGRP "J_CLK" 30 ns                 |            |            |      
--------------------------------------------------------------------------------
  TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" | 15.000ns   | 2.373ns    | 0    
   TO TIMEGRP "