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Project Navigator Auto-Make Log File
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Project Navigator Auto-Make Log File
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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:3498 - No primary, secondary unit in the file "F:/vhdlproject/vhdl0716/fifo_rs232.vhd. Ignore this file from project file "top_fmdm_project_vhdl.prj".
Compiling vhdl file "F:/vhdlproject/vhdl0716/baud.vhd" in Library work.
Entity <baud> compiled.
Entity <baud> (Architecture <Behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/reciever.vhd" in Library work.
Entity <reciever> compiled.
Entity <reciever> (Architecture <Behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/transfer.vhd" in Library work.
Entity <transfer> compiled.
Entity <transfer> (Architecture <Behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/top_uart.vhd" in Library work.
Entity <top_uart> compiled.
Entity <top_uart> (Architecture <Behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/select_clk.vhd" in Library work.
Entity <select_clk> compiled.
Entity <select_clk> (Architecture <Behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/adc_control.vhd" in Library work.
Entity <adc_control> compiled.
Entity <adc_control> (Architecture <Behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/add_accumulator.vhd" in Library work.
Entity <add_accumulator> compiled.
Entity <add_accumulator> (Architecture <Behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/accumulator_ctr_dataadjust.vhd" in Library work.
Entity <accumulator_ctr_dataadjust> compiled.
Entity <accumulator_ctr_dataadjust> (Architecture <Behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/dataformat_adjust_log.vhd" in Library work.
Entity <dataformat_adjust_log> compiled.
Entity <dataformat_adjust_log> (Architecture <Behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/dataformat_adjust_narrowfreq.vhd" in Library work.
Entity <dataformat_adjust_narrowfreq> compiled.
Entity <dataformat_adjust_narrowfreq> (Architecture <Behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/dataformat_adjust_widefreq.vhd" in Library work.
Entity <dataformat_adjust_widefreq> compiled.
Entity <dataformat_adjust_widefreq> (Architecture <Behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/mux_log_wide_narrow.vhd" in Library work.
Entity <mux_log_wide_narrow> compiled.
Entity <mux_log_wide_narrow> (Architecture <Behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/readfifo_rs232.vhd" in Library work.
Entity <readfifo_RS232> compiled.
Entity <readfifo_RS232> (Architecture <Behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" in Library work.
Entity <narrow_wide_pulse_generate> compiled.
Entity <narrow_wide_pulse_generate> (Architecture <behavioral>) compiled.
Compiling vhdl file "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd" in Library work.
Entity <top_fmdm_project> compiled.
Entity <top_fmdm_project> (Architecture <Behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <top_fmdm_project> (Architecture <Behavioral>).
WARNING:Xst:766 - "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd" line 221: Generating a Black Box for component <BUFG>.
WARNING:Xst:753 - "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd" line 268: Unconnected output port 'mux_en' of component 'dataformat_adjust_narrowfreq'.
WARNING:Xst:753 - "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd" line 275: Unconnected output port 'mux_en' of component 'dataformat_adjust_widefreq'.
WARNING:Xst:753 - "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd" line 291: Unconnected output port 'full' of component 'fifo_rs232'.
WARNING:Xst:766 - "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd" line 291: Generating a Black Box for component <fifo_rs232>.
Entity <top_fmdm_project> analyzed. Unit <top_fmdm_project> generated.

Analyzing Entity <top_uart> (Architecture <behavioral>).
WARNING:Xst:1542 - "F:/vhdlproject/vhdl0716/top_uart.vhd" line 78: No default binding for component: <reciever>. Generic <framlenr> is not on the component.
WARNING:Xst:1542 - "F:/vhdlproject/vhdl0716/top_uart.vhd" line 85: No default binding for component: <transfer>. Generic <framlent> is not on the component.
Entity <top_uart> analyzed. Unit <top_uart> generated.

Analyzing Entity <baud> (Architecture <behavioral>).
Entity <baud> analyzed. Unit <baud> generated.

Analyzing Entity <reciever> (Architecture <behavioral>).
Entity <reciever> analyzed. Unit <reciever> generated.

Analyzing Entity <transfer> (Architecture <behavioral>).
Entity <transfer> analyzed. Unit <transfer> generated.

Analyzing Entity <select_clk> (Architecture <behavioral>).
Entity <select_clk> analyzed. Unit <select_clk> generated.

Analyzing Entity <adc_control> (Architecture <behavioral>).
Entity <adc_control> analyzed. Unit <adc_control> generated.

Analyzing Entity <add_accumulator> (Architecture <behavioral>).
Entity <add_accumulator> analyzed. Unit <add_accumulator> generated.

Analyzing Entity <accumulator_ctr_dataadjust> (Architecture <behavioral>).
Entity <accumulator_ctr_dataadjust> analyzed. Unit <accumulator_ctr_dataadjust> generated.

Analyzing Entity <dataformat_adjust_log> (Architecture <behavioral>).
Entity <dataformat_adjust_log> analyzed. Unit <dataformat_adjust_log> generated.

Analyzing Entity <dataformat_adjust_narrowfreq> (Architecture <behavioral>).
Entity <dataformat_adjust_narrowfreq> analyzed. Unit <dataformat_adjust_narrowfreq> generated.

Analyzing Entity <dataformat_adjust_widefreq> (Architecture <behavioral>).
Entity <dataformat_adjust_widefreq> analyzed. Unit <dataformat_adjust_widefreq> generated.

Analyzing Entity <mux_log_wide_narrow> (Architecture <behavioral>).
Entity <mux_log_wide_narrow> analyzed. Unit <mux_log_wide_narrow> generated.

Analyzing Entity <readfifo_RS232> (Architecture <behavioral>).
Entity <readfifo_RS232> analyzed. Unit <readfifo_RS232> generated.

Analyzing Entity <narrow_wide_pulse_generate> (Architecture <behavioral>).
Entity <narrow_wide_pulse_generate> analyzed. Unit <narrow_wide_pulse_generate> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <transfer>.
    Related source file is "F:/vhdlproject/vhdl0716/transfer.vhd".
    Found finite state machine <FSM_0> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 11                                             |
    | Inputs             | 4                                              |
    | Outputs            | 5                                              |
    | Clock              | bclkt (rising_edge)                            |
    | Reset              | resett (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | x_idle                                         |
    | Power Up State     | x_idle                                         |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <txd_done>.
    Found 5-bit comparator greatequal for signal <$n0006> created at line 68.
    Found 5-bit comparator greatequal for signal <$n0007> created at line 78.
    Found 5-bit adder for signal <$n0018> created at line 58.
    Found 32-bit adder for signal <$n0019> created at line 92.
    Found 1-bit register for signal <txds>.
    Found 32-bit register for signal <xbitcnt>.
    Found 5-bit register for signal <xcnt16>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  39 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   2 Comparator(s).
Unit <transfer> synthesized.


Synthesizing Unit <reciever>.
    Related source file is "F:/vhdlproject/vhdl0716/reciever.vhd".
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 5                                              |
    | Clock              | bclkr (rising_edge)                            |
    | Reset              | resetr (negative)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | r_start                                        |
    | Power Up State     | r_start                                        |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <rbuf>.
    Found 1-bit register for signal <r_ready>.
    Found 4-bit comparator greatequal for signal <$n0006> created at line 62.
    Found 4-bit adder for signal <$n0024> created at line 39.
    Found 32-bit adder for signal <$n0025> created at line 75.
    Found 4-bit register for signal <count>.
    Found 8-bit register for signal <rbufs>.
    Found 32-bit register for signal <rcnt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  53 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <reciever> synthesized.


Synthesizing Unit <baud>.
    Related source file is "F:/vhdlproject/vhdl0716/baud.vhd".
    Found 1-bit register for signal <baud_bclk>.
    Found 32-bit comparator greatequal for signal <$n0006> created at line 45.
    Found 32-bit comparator less for signal <$n0007> created at line 45.
    Found 32-bit up counter for signal <cnt>.
    Summary:
	inferred   1 Counter(s).
	inferred   1 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <baud> synthesized.


Synthesizing Unit <narrow_wide_pulse_generate>.
    Related source file is "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd".
    Found finite state machine <FSM_2> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | log                                            |
    | Power Up State     | log                                            |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <narrow_wide_pulse>.
    Found 32-bit comparator greatequal for signal <$n0004> created at line 70.
    Found 32-bit comparator greater for signal <$n0005> created at line 79.
    Found 32-bit comparator greatequal for signal <$n0006> created at line 88.
    Found 32-bit adder for signal <$n0012> created at line 68.
    Found 32-bit register for signal <cnt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  33 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   3 Comparator(s).
Unit <narrow_wide_pulse_generate> synthesized.


Synthesizing Unit <readfifo_RS232>.
    Related source file is "F:/vhdlproject/vhdl0716/readfifo_rs232.vhd".
    Register <trans_com> equivalent to <fifo_enable> has been removed
    Found finite state machine <FSM_3> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 2                                              |
    | Outputs            | 1                                              |
    | Clock              | rs232_clk_read (rising_edge)                   |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <fifo_enable>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 D-type flip-flop(s).
Unit <readfifo_RS232> synthesized.


Synthesizing Unit <mux_log_wide_narrow>.
    Related source file is "F:/vhdlproject/vhdl0716/mux_log_wide_narrow.vhd".
WARNING:Xst:646 - Signal <command<4:0>> is assigned but never used.
WARNING:Xst:737 - Found 8-bit latch for signal <dataout_mux>.
    Found 8-bit 4-to-1 multiplexer for signal <$n0002>.
    Found 8-bit 4-to-1 multiplexer for signal <$n0005>.
    Found 8-bit register for signal <command>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred  16 Multiplexer(s).
Unit <mux_log_wide_narrow> synthesized.


Synthesizing Unit <dataformat_adjust_widefreq>.
    Related source file is "F:/vhdlproject/vhdl0716/dataformat_adjust_widefreq.vhd".
WARNING:Xst:647 - Input <data_in<5:0>> is never used.
    Found finite state machine <FSM_4> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 5                                              |
    | Inputs             | 1                                              |
    | Outputs            | 4                                              |