__projnav.log
来自「ISE7.1」· LOG 代码 · 共 1,605 行 · 第 1/5 页
LOG
1,605 行
| Clock | select_clk (rising_edge) | | Reset | reset (negative) | | Reset type | synchronous | | Reset State | x_wait | | Power Up State | x_wait | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 8-bit register for signal <dataout_widefreq>. Found 1-bit register for signal <mux_en>. Found 8-bit register for signal <data1>. Found 8-bit register for signal <data2>. Summary: inferred 1 Finite State Machine(s). inferred 25 D-type flip-flop(s).Unit <dataformat_adjust_widefreq> synthesized.Synthesizing Unit <dataformat_adjust_narrowfreq>. Related source file is "F:/vhdlproject/vhdl0716/dataformat_adjust_narrowfreq.vhd".WARNING:Xst:647 - Input <data_in<5:0>> is never used. Found finite state machine <FSM_5> for signal <state>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 5 | | Inputs | 1 | | Outputs | 4 | | Clock | select_clk (rising_edge) | | Reset | reset (negative) | | Reset type | synchronous | | Reset State | x_wait | | Power Up State | x_wait | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <mux_en>. Found 8-bit register for signal <dataout_narrowfreq>. Found 8-bit register for signal <data1>. Found 8-bit register for signal <data2>. Summary: inferred 1 Finite State Machine(s). inferred 25 D-type flip-flop(s).Unit <dataformat_adjust_narrowfreq> synthesized.Synthesizing Unit <dataformat_adjust_log>. Related source file is "F:/vhdlproject/vhdl0716/dataformat_adjust_log.vhd".WARNING:Xst:647 - Input <data_in<5:0>> is never used. Found finite state machine <FSM_6> for signal <state>. ----------------------------------------------------------------------- | States | 4 | | Transitions | 5 | | Inputs | 1 | | Outputs | 4 | | Clock | select_clk (rising_edge) | | Reset | reset (negative) | | Reset type | synchronous | | Reset State | x_wait | | Power Up State | x_wait | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 1-bit register for signal <mux_en>. Found 8-bit register for signal <dataout_log>. Found 8-bit register for signal <data1>. Found 8-bit register for signal <data2>. Summary: inferred 1 Finite State Machine(s). inferred 25 D-type flip-flop(s).Unit <dataformat_adjust_log> synthesized.Synthesizing Unit <accumulator_ctr_dataadjust>. Related source file is "F:/vhdlproject/vhdl0716/accumulator_ctr_dataadjust.vhd". Found 1-bit register for signal <accumulator_clr_clk>. Found 1-bit register for signal <accumulator_send_clk>. Found 10-bit comparator greatequal for signal <$n0005> created at line 60. Found 10-bit comparator greatequal for signal <$n0007> created at line 47. Found 10-bit up counter for signal <accumulator_clr_clk_counter>. Found 10-bit up counter for signal <accumulator_send_clk_counter>. Summary: inferred 2 Counter(s). inferred 2 D-type flip-flop(s). inferred 2 Comparator(s).Unit <accumulator_ctr_dataadjust> synthesized.Synthesizing Unit <add_accumulator>. Related source file is "F:/vhdlproject/vhdl0716/add_accumulator.vhd". Found 22-bit register for signal <Q>. Found 22-bit adder for signal <$n0002> created at line 55. Found 22-bit register for signal <q_buf>. Summary: inferred 44 D-type flip-flop(s). inferred 1 Adder/Subtractor(s).Unit <add_accumulator> synthesized.Synthesizing Unit <adc_control>. Related source file is "F:/vhdlproject/vhdl0716/adc_control.vhd". Found 12-bit register for signal <data_out_toaccumulator>. Found 12-bit subtractor for signal <$n0000> created at line 65. Summary: inferred 12 D-type flip-flop(s). inferred 1 Adder/Subtractor(s).Unit <adc_control> synthesized.Synthesizing Unit <select_clk>. Related source file is "F:/vhdlproject/vhdl0716/select_clk.vhd".WARNING:Xst:646 - Signal <command<7:5>> is assigned but never used. Found 8-bit register for signal <command>. Summary: inferred 8 D-type flip-flop(s).Unit <select_clk> synthesized.Synthesizing Unit <top_uart>. Related source file is "F:/vhdlproject/vhdl0716/top_uart.vhd".Unit <top_uart> synthesized.Synthesizing Unit <top_fmdm_project>. Related source file is "F:/vhdlproject/vhdl0716/top_fmdm_project.vhd".Unit <top_fmdm_project> synthesized.INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Analyzing FSM <FSM_6> for best encoding.Optimizing FSM <FSM_6> on signal <state[1:2]> with gray encoding.------------------------ State | Encoding------------------------ x_wait | 00 adjust | 01 send_data1 | 11 send_data2 | 10------------------------Analyzing FSM <FSM_5> for best encoding.Optimizing FSM <FSM_5> on signal <state[1:2]> with gray encoding.------------------------ State | Encoding------------------------ x_wait | 00 adjust | 01 send_data1 | 11 send_data2 | 10------------------------Analyzing FSM <FSM_4> for best encoding.Optimizing FSM <FSM_4> on signal <state[1:2]> with gray encoding.------------------------ State | Encoding------------------------ x_wait | 00 adjust | 01 send_data1 | 11 send_data2 | 10------------------------Analyzing FSM <FSM_3> for best encoding.Optimizing FSM <FSM_3> on signal <state[1:2]> with sequential encoding.---------------------------------- State | Encoding---------------------------------- idle | 00 rd_en_trcom_generate | 01 cmd_cancel | 10----------------------------------Analyzing FSM <FSM_2> for best encoding.Optimizing FSM <FSM_2> on signal <state[1:2]> with sequential encoding.-------------------- State | Encoding-------------------- log | 00 narrow | 01 wide | 10--------------------Analyzing FSM <FSM_1> for best encoding.Optimizing FSM <FSM_1> on signal <state[1:3]> with sequential encoding.---------------------- State | Encoding---------------------- r_start | 000 r_center | 001 r_wait | 010 r_sample | 100 r_stop | 011----------------------Analyzing FSM <FSM_0> for best encoding.Optimizing FSM <FSM_0> on signal <state[1:5]> with speed1 encoding.--------------------- State | Encoding--------------------- x_idle | 10000 x_start | 01000 x_wait | 00100 x_shift | 00001 x_stop | 00010---------------------Dynamic shift register inference ...=========================================================================HDL Synthesis ReportMacro Statistics# FSMs : 7# Adders/Subtractors : 11 12-bit subtractor : 3 22-bit adder : 3 32-bit adder : 3 4-bit adder : 1 5-bit adder : 1# Counters : 3 10-bit up counter : 2 32-bit up counter : 1# Registers : 63 1-bit register : 37 12-bit register : 3 22-bit register : 6 32-bit register : 3 4-bit register : 1 5-bit register : 1 8-bit register : 12# Latches : 1 8-bit latch : 1# Comparators : 10 10-bit comparator greatequal : 2 32-bit comparator greatequal : 3 32-bit comparator greater : 1 32-bit comparator less : 1 4-bit comparator greatequal : 1 5-bit comparator greatequal : 2# Multiplexers : 2 8-bit 4-to-1 multiplexer : 2==================================================================================================================================================* Low Level Synthesis *=========================================================================Executing edif2ngd -noa "fifo_rs232.edn" "fifo_rs232.ngo"Release 7.1.04i - edif2ngd H.42Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.INFO:NgdBuild - Release 7.1.04i edif2ngd H.42INFO:NgdBuild - Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.Writing module to "fifo_rs232.ngo"...Loading core <fifo_rs232> for timing and area information for instance <fifo>.WARNING:Xst:1291 - FF/Latch <command_7> is unconnected in block <select_clk>.WARNING:Xst:1291 - FF/Latch <command_5> is unconnected in block <select_clk>.WARNING:Xst:1291 - FF/Latch <command_6> is unconnected in block <select_clk>.WARNING:Xst:1291 - FF/Latch <command_0> is unconnected in block <mux_log_wide_narrow>.WARNING:Xst:1291 - FF/Latch <command_1> is unconnected in block <mux_log_wide_narrow>.WARNING:Xst:1291 - FF/Latch <command_2> is unconnected in block <mux_log_wide_narrow>.WARNING:Xst:1291 - FF/Latch <command_3> is unconnected in block <mux_log_wide_narrow>.WARNING:Xst:1291 - FF/Latch <command_4> is unconnected in block <mux_log_wide_narrow>.WARNING:Xst:1291 - FF/Latch <Q_0> is unconnected in block <acumulator_log>.WARNING:Xst:1291 - FF/Latch <Q_1> is unconnected in block <acumulator_log>.WARNING:Xst:1291 - FF/Latch <Q_2> is unconnected in block <acumulator_log>.WARNING:Xst:1291 - FF/Latch <Q_3> is unconnected in block <acumulator_log>.WARNING:Xst:1291 - FF/Latch <Q_4> is unconnected in block <acumulator_log>.WARNING:Xst:1291 - FF/Latch <Q_5> is unconnected in block <acumulator_log>.WARNING:Xst:1291 - FF/Latch <Q_0> is unconnected in block <acumulator_wide>.WARNING:Xst:1291 - FF/Latch <Q_1> is unconnected in block <acumulator_wide>.WARNING:Xst:1291 - FF/Latch <Q_2> is unconnected in block <acumulator_wide>.WARNING:Xst:1291 - FF/Latch <Q_3> is unconnected in block <acumulator_wide>.WARNING:Xst:1291 - FF/Latch <Q_4> is unconnected in block <acumulator_wide>.WARNING:Xst:1291 - FF/Latch <Q_5> is unconnected in block <acumulator_wide>.WARNING:Xst:1291 - FF/Latch <Q_0> is unconnected in block <acumulator_narrow>.WARNING:Xst:1291 - FF/Latch <Q_1> is unconnected in block <acumulator_narrow>.WARNING:Xst:1291 - FF/Latch <Q_2> is unconnected in block <acumulator_narrow>.WARNING:Xst:1291 - FF/Latch <Q_3> is unconnected in block <acumulator_narrow>.WARNING:Xst:1291 - FF/Latch <Q_4> is unconnected in block <acumulator_narrow>.WARNING:Xst:1291 - FF/Latch <Q_5> is unconnected in block <acumulator_narrow>.WARNING:Xst:1291 - FF/Latch <mux_en> is unconnected in block <data_adjust_narrow>.WARNING:Xst:1291 - FF/Latch <mux_en> is unconnected in block <data_adjust_wide>.WARNING:Xst:1988 - Unit <baud>: instances <Mcompar__n0006>, <Mcompar__n0007> of unit <LPM_COMPARE_4> and unit <LPM_COMPARE_5> are dual, second instance is removedOptimizing unit <top_fmdm_project> ...Optimizing unit <dataformat_adjust_widefreq> ...Optimizing unit <readfifo_RS232> ...Optimizing unit <narrow_wide_pulse_generate> ...Optimizing unit <accumulator_ctr_dataadjust> ...Optimizing unit <mux_log_wide_narrow> ...Optimizing unit <baud> ...Optimizing unit <reciever> ...Optimizing unit <dataformat_adjust_narrowfreq> ...Optimizing unit <transfer> ...WARNING:Xst:1293 - FF/Latch <xcnt16_4> has a constant value of 0 in block <transfer>.Optimizing unit <select_clk> ...Optimizing unit <dataformat_adjust_log> ...Optimizing unit <add_accumulator> ...Loading device for application Rf_Device from file '2v500.nph' in environment D:/Xilinx.Mapping all equations...WARNING:Xst:1291 - FF/Latch <data_adjust_wide/mux_en> is unconnected in block <top_fmdm_project>.WARNING:Xst:1291 - FF/Latch <data_adjust_narrow/mux_en> is unconnected in block <top_fmdm_project>.WARNING:Xst:1291 - FF/Latch <acumulator_narrow/Q_0> is unconnected in block <top_fmdm_project>.WARNING:Xst:1291 - FF/Latch <acumulator_narrow/Q_1> is unconnected in block <top_fmdm_project>.WARNING:Xst:1291 - FF/Latch <acumulator_narrow/Q_2> is unconnected in block <top_fmdm_project>.WARNING:Xst:1291 - FF/Latch <acumulator_narrow/Q_3> is unconnected in block <top_fmdm_project>.WARNING:Xst:1291 - FF/Latch <acumulator_narrow/Q_4> is unconnected in block <top_fmdm_project>.WARNING:Xst:1291 - FF/Latch <acumulator_narrow/Q_5> is unconnected in block <top_fmdm_project>.WARNING:Xst:1291 - FF/Latch <acumulator_wide/Q_0> is unconnected in block <top_fmdm_project>.⌨️ 快捷键说明
复制代码Ctrl + C
搜索代码Ctrl + F
全屏模式F11
增大字号Ctrl + =
减小字号Ctrl + -
显示快捷键?