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LOG
1,605 行
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" in Library work.Entity <narrow_wide_pulse_generate> compiled.ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 57. parse error, unexpected OPENPAR, expecting SEMICOLON or IS--> Total memory usage is 77572 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" in Library work.Entity <narrow_wide_pulse_generate> compiled.ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 58. parse error, unexpected END--> Total memory usage is 77152 kilobytesNumber of errors : 1 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" in Library work.Entity <narrow_wide_pulse_generate> compiled.Entity <narrow_wide_pulse_generate> (Architecture <Behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <narrow_wide_pulse_generate> (Architecture <Behavioral>).Entity <narrow_wide_pulse_generate> analyzed. Unit <narrow_wide_pulse_generate> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <narrow_wide_pulse_generate>. Related source file is "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd".WARNING:Xst:647 - Input <clk> is never used.WARNING:Xst:647 - Input <reset> is never used.WARNING:Xst:1306 - Output <narrow_wide_pulse> is never assigned.Unit <narrow_wide_pulse_generate> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <narrow_wide_pulse_generate> ...Loading device for application Rf_Device from file '2v500.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block narrow_wide_pulse_generate, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2v500fg456-4 Number of bonded IOBs: 3 out of 264 1% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" in Library work.Entity <narrow_wide_pulse_generate> compiled.Entity <narrow_wide_pulse_generate> (Architecture <behavioral>) compiled.=========================================================================* HDL Analysis *=========================================================================Analyzing Entity <narrow_wide_pulse_generate> (Architecture <behavioral>).Entity <narrow_wide_pulse_generate> analyzed. Unit <narrow_wide_pulse_generate> generated.=========================================================================* HDL Synthesis *=========================================================================Synthesizing Unit <narrow_wide_pulse_generate>. Related source file is "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd".WARNING:Xst:647 - Input <clk> is never used.WARNING:Xst:647 - Input <reset> is never used.WARNING:Xst:1306 - Output <narrow_wide_pulse> is never assigned.WARNING:Xst:1780 - Signal <state> is never used or assigned.Unit <narrow_wide_pulse_generate> synthesized.=========================================================================* Advanced HDL Synthesis *=========================================================================Advanced RAM inference ...Advanced multiplier inference ...Advanced Registered AddSub inference ...Dynamic shift register inference ...=========================================================================HDL Synthesis ReportFound no macro==================================================================================================================================================* Low Level Synthesis *=========================================================================Optimizing unit <narrow_wide_pulse_generate> ...Loading device for application Rf_Device from file '2v500.nph' in environment D:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block narrow_wide_pulse_generate, actual ratio is 0.=========================================================================* Final Report *=========================================================================Device utilization summary:---------------------------Selected Device : 2v500fg456-4 Number of bonded IOBs: 3 out of 264 1% =========================================================================TIMING REPORTClock Information:------------------No clock signals found in this designTiming Summary:---------------Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found=========================================================================
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================Compiling vhdl file "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" in Library work.Entity <narrow_wide_pulse_generate> compiled.ERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 69. parse error, unexpected ROWERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 78. parse error, unexpected WHEN, expecting ENDERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 83. parse error, unexpected ELSE, expecting ENDERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 86. parse error, unexpected IF, expecting PROCESSERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 92. parse error, unexpected ELSE, expecting ENDERROR:HDLParsers:164 - "F:/vhdlproject/vhdl0716/narrow_wide_pulse_generate.vhd" Line 95. parse error, unexpected IF, expecting PROCESS--> Total memory usage is 77152 kilobytesNumber of errors : 6 ( 0 filtered)Number of warnings : 0 ( 0 filtered)Number of infos : 0 ( 0 filtered)ERROR: XST failedProcess "Synthesize" did not complete.
Project Navigator Auto-Make Log File-------------------------------------
Started process "Synthesize".=========================================================================* HDL Compilation *=========================================================================⌨️ 快捷键说明
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