control.v

一个SDH中最基本传输模块STM-1的帧头检测器

module control(
               //input
               din,
               clk,
               rst_n,
               head,
               position,
               //dout
               lof,
               fp,
               dout
               );
               
  input  [15:0]  din;             
  input          clk;
  input          rst_n;
  input          head;
  input  [3:0]   position;
  
  output         lof;
  output         fp;
  output [7:0]   dout;
  
  reg  [4:0]  cnt_data;
  reg  [5:0]  state;
  reg         lof;
  reg         fp;
  reg  [7:0]  dout;
  reg  [3:0]  place;
    
  parameter desynchron=6'b000001;
  parameter find1=6'b000010;
  parameter find2=6'b000100;
  parameter synchron=6'b001000;
  parameter lose1=6'b010000;
  parameter lose2=6'b100000;

  
  always @(posedge clk or negedge rst_n)
    if(!rst_n)
      cnt_data <= 0;
    else if(head&&lof)
      cnt_data <= 1;
    else if(cnt_data != 28)
      cnt_data <= cnt_data +1;
    else
      cnt_data <= 1;
      
  always @(posedge clk or negedge rst_n)
    if(!rst_n)
      state <= desynchron;
    else begin    
           case(state)
             desynchron: if(head)
                           state <= find1;
             find1:      if(head && cnt_data==28)
                           state <= find2;
                         else if(cnt_data==28 && !head)
                           state <= desynchron;
             find2:      if(head && cnt_data==28)
                           state <= synchron;
                         else if(cnt_data==28 && !head)
                           state <= desynchron;   
             synchron:   if(cnt_data==28 && !head)
                           state <= lose1;
                         else if(head && cnt_data==28)
                           state <= synchron;
             lose1:      if(cnt_data==28 && !head)
                           state <= lose2;
                         else if(head && cnt_data==28)
                           state <= synchron;
             lose2:      if(cnt_data==28 && !head)
                           state <= desynchron;
                         else if(head && cnt_data==28)
                           state <= synchron;
             default:   state <= desynchron;
           endcase
         end
      
  always @(posedge clk or negedge rst_n)
    if(!rst_n)
      lof <= 1;
    else if((state == synchron) && head)
      lof <= 0;
    else if(state == desynchron)
      lof <= 1;

  always @(posedge clk or negedge rst_n)
    if(!rst_n)
      fp <= 0;
    else if(cnt_data==28)
      fp <= 1;
    else 
      fp <= 0;
      
  always @(posedge clk or negedge rst_n)
    if(!rst_n)
      place <= 0;
    else if((state == synchron) && head)
      place <= position;

  always @(posedge clk or negedge rst_n)
    if(!rst_n)   
      dout <= 8'b0;
    else if(cnt_data<22||cnt_data>27)begin
      case(place)
           0: dout<=din[7:0];
           1: dout<=din[8:1];
           2: dout<=din[9:2];
           3: dout<=din[10:3];
           4: dout<=din[11:4];
           5: dout<=din[12:5];      
           6: dout<=din[13:6];
           7: dout<=din[14:7];
           8: dout<=din[15:8];
           default: dout <= 8'b0;
         endcase
    end  

       
endmodule