sdh.v

来自「一个SDH中最基本传输模块STM-1的帧头检测器」· Verilog 代码 · 共 64 行

module sdh(
           //input
           din,
           clk,
           rst_n,
           //output
           lof,
           fp,
           dout
           );
           
  input  [7:0]  din;
  input         clk;
  input         rst_n;
  
  output        lof;
  output        fp;
  output [7:0]  dout;
  
  wire          head;
  wire   [3:0]  position;
  wire   [15:0] din16;  

  buffer buffer(
               //input
               .din(din),
               .clk(clk),
               .rst_n(rst_n),
               //output
               .dout(din16)
               );
  
  find_head find_head(
                   //input
                   .din(din16),
                   .clk(clk),
                   .rst_n(rst_n),
                   //output
                   .head(head),
                   .position(position)
                   );
       
	control control(
	               //input
	               .din(din16),
	               .clk(clk),
	               .rst_n(rst_n),
	               .head(head),
	               .position(position),
	               //dout
	               .lof(lof),
	               .fp(fp),
	               .dout(dout)
	               );
	               

endmodule