test_sdh.v

一个SDH中最基本传输模块STM-1的帧头检测器

module test_sdh();

	reg clk,rst_n;
	reg [7:0] din;
	wire fp,lof;
	wire [7:0] dout;
	integer i;
	initial begin
		rst_n=1;
		#10 rst_n =0;
		#10 rst_n =1;
	end
	
	initial begin
		clk=1;
		forever #5 clk=~clk;
	end

	initial begin
		din=0;
		
		#50 din=0;
    sendhead;
    sendhead;
    sendhead;
    
		sendhead;
    sendhead;    
    sendhead; 

    #10 sendhead;
     sendhead;
     sendhead;
     sendhead;
    sendhead;
    
    
    #10 din=0;
    #100 sendhead2;
    sendhead2;
    sendhead2;
    
		sendhead2;
    sendhead2;    
    sendhead2; 

    #10 sendhead2;
     sendhead2;
     sendhead2;
     sendhead2;
    sendhead2;
		#1000 $finish ;
	end

  sdh sdh(
          //input
          .din(din),
          .clk(clk),
          .rst_n(rst_n),
          //output
	        .lof(lof),
	        .fp(fp),
	         .dout(dout)
           ); 
          
  initial begin
  	$fsdbDumpfile("test_sdh.fsdb");
  	$fsdbDumpvars;
  end
  
  
  task sendhead;
    begin
	  #10 din=8'hf6;
			#10 din=8'hf6;
			#10 din=8'hf6;
			#10 din=8'h28;
			#10 din=8'h28;
			#10 din=8'h28;
			#10 din=8'h1;
			for (i=1;i<22;i=i+1)
			 #10 din=din+1;
		end
  endtask
  
   task sendhead2;
    begin
			 #10 din=8'h0f;
			#10 din=8'h6f;
			#10 din=8'h6f;
			#10 din=8'h62;
			#10 din=8'h82;
			#10 din=8'h82;
			#10 din=8'h80;
			#10 din=8'h1;
			for (i=1;i<21;i=i+1)
			 #10 din=din+1;
		end
  endtask 
endmodule