hdlc.fit.summary

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

Flow Status : Successful - Sun Jul 01 22:51:48 2007
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : hdlc
Top-level Entity Name : hdlc
Family : Cyclone
Device : EP1C3T100C6
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 123 / 2,910 ( 4 % )
Total pins : 17 / 65 ( 26 % )
Total virtual pins : 0
Total memory bits : 0 / 59,904 ( 0 % )
Total PLLs : 0 / 1 ( 0 % )