hdlc.sim.qmsg

该工程是基于verilog hdl 语言编写的帧传输协议HDLC帧的发送端代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 01 23:11:54 2007 " "Info: Processing started: Sun Jul 01 23:11:54 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off hdlc -c hdlc " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off hdlc -c hdlc" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|control:control1\|sel1 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|control:control1\|sel1\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|control:control1\|sel2 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|control:control1\|sel2\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|control:control1\|en2 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|control:control1\|en2\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[15\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[15\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[14\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[14\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[13\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[13\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[12\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[12\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[11\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[11\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[10\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[10\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[9\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[9\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[8\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[8\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[7\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[7\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[6\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[6\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[5\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[5\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[4\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[4\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[3\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[3\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[2\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[2\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[1\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[1\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|shift32:shift\|crc_reg\[0\] 5.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 5.0 ns on register \"\|hdlc\|shift32:shift\|crc_reg\[0\]\"" {  } {  } 0}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|hdlc\|free:free1\|count\[0\] 935.0 ns " "Warning: Found clock-sensitive change during active clock edge at time 935.0 ns on register \"\|hdlc\|free:free1\|count\[0\]\"" {  } {  } 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     83.90 % " "Info: Simulation coverage is      83.90 %" {  } {  } 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "27215 " "Info: Number of transitions in simulation is 27215" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 20 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 01 23:11:55 2007 " "Info: Processing ended: Sun Jul 01 23:11:55 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}
{ "Info" "ICPT_EVAL_MODE" "3 04-jul-2007 " "Info: You are using the Quartus II software in \"Evaluation Mode\". You have 3 days left (until 04-jul-2007) before compilation and simulation support are disabled." {  } {  } 0}