control.v

来自「硬件编程实现伪随机交织器和随机交织器」· Verilog 代码 · 共 16 行

module control (addrin,countin,datein,clk,dateout,addrout);

input [2:0] addrin;
input [2:0] countin;
input clk,datein;
output dateout;
output [2:0] addrout;





assign dateout=(!clk)? datein:1'bz;
assign addrout=(clk)?addrin:countin;

endmodule