jie.v

来自「硬件编程实现伪随机交织器和随机交织器」· Verilog 代码 · 共 16 行

module jie(datein,datejie,addr,addrin,clk1,clk);
   input datein,clk,clk1;
   input [2:0]addr;
   input [2:0]addrin;
   output datejie;
   reg ram [6:0];
  
    assign datejie = (!clk)? ram[addrin]:1'hz;

  always @(posedge clk1)
    begin
     if(clk)
     ram[addr]<=datein;
    end
  endmodule