ram.v

来自「硬件编程实现伪随机交织器和随机交织器」· Verilog 代码 · 共 15 行

module ram(date,dateout,addr,ena,read,write);
   input date;
   input [2:0]addr;
   input ena;
   input read,write;
   output dateout;
   reg ram [6:0];
  
    assign dateout = (read&&ena)? ram[addr]:1'hz;

  always @(posedge write)
    begin
   ram[addr]<=date;
    end
  endmodule