counter.v

来自「硬件编程实现伪随机交织器和随机交织器」· Verilog 代码 · 共 24 行

module counter (clkin,clkin1,countout);

input clkin,clkin1;
output [2:0] countout;


reg  [2:0] countout;


always@(posedge clkin1 )

if(!clkin)

 begin
  if(countout<6)
countout<=countout+1;
  else
 countout<=0;
  end
 else
countout<=0;
endmodule