phase_reg.vhd

来自「这是用VHDL语言编写的一个DDS频率合成器的源程序」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity phase_reg is
port
(
	clk	:in std_logic;
	--WE	:in std_logic;
	reset:in std_logic;
	Datain	:in std_logic_vector ( 16 downto 0);
	Dataout	:out std_logic_vector (16 downto 0)
);
end phase_reg;

architecture behave of phase_reg is
signal buff:std_logic_vector (16 downto 0);
begin
	process(clk)
	begin
		if (clk'event and clk='0') then
			if (reset='1') then buff<="00000000000000000";
			else buff<=Datain;
			end if;
		end if;
	end process;
	Dataout<=buff;
end behave;