antishake1.vhd

来自「这是用VHDL语言编写的一个DDS频率合成器的源程序」· VHDL 代码 · 共 25 行

library ieee;
use ieee.std_logic_1164.all;

entity antishake1 is
port
(
	sin		:in std_logic;
	clk		:in std_logic;
	sout	:out std_logic
);
end antishake1;

architecture behave of antishake1 is
signal s1,s2:std_logic;
begin
	sout <= s1 and (not (s2));
	process(clk)
	begin
		if (clk'event and clk='0') then
			s1<=sin;
			s2<=s1;
		end if;
	end process;
end behave;