delay.vhd

来自「这是用VHDL语言编写的一个DDS频率合成器的源程序」· VHDL 代码 · 共 28 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity delay is
port
(
	sin		:in std_logic;
	clk		:in std_logic;
	sout	:buffer std_logic
);
end delay;

architecture behave of delay is
signal s1:std_logic_vector (3 downto 0);
begin
	process(clk)
	begin
		if (clk'event and clk='0') then
			if (sin='1' and s1="0000") then sout<='1';
			elsif (sout='1' and s1<"1110") then s1<=s1+1; 
			else sout<='0';s1<="0000";
			end if;
		end if;
	end process;
end behave;