antishake.vhd

来自「这是用VHDL语言编写的一个DDS频率合成器的源程序」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity antishake is
port
(
	clk	:in std_logic;
	sin	:in std_logic_vector (3 downto 0);
	sout:out std_logic_vector (3 downto 0)
);
end antishake;

architecture behave of antishake is
signal s1,s2:std_logic_vector (3 downto 0);
begin
	sout <= s1 and (not (s2));
	process(clk)
	begin
		if (clk'event and clk='1') then
			s1<=sin;
			s2<=s1;
		end if;
	end process;
end behave;