freqdiv.vhd

来自「这是用VHDL语言编写的一个DDS频率合成器的源程序」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity freqdiv is
port
(
	clk	:in std_logic;
	clk_out	:buffer std_logic
);
end freqdiv;

architecture behave of freqdiv is
signal num: std_logic_vector(7 downto 0);
begin
	process(clk)
	begin
		if (clk'event and clk='1') then
			if (num="00000111") then 
				num<="00000000";
				clk_out	<=not clk_out;
			else num<=num+1;
			end if;
			--if (num="00000111") then clk_out<=not clk_out;
			
			--elsif (num="00001110") then clk_out<=not clk_out;
			--num<="00000000";
			--else num<=num+1;
			
			
		end if;
	end process;
end behave;