control.v

FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波

//name:control.v       主控模块 	2006-5-1	version:1.0		作者：田世坤
//									2006-9-2	version:1.1		作者：田世坤
//波形输出主控模块：
//输入：ClkIn10mhz：系统时钟(10MHz);	

//输出：DLedout：发光二极管，八位宽;
//      Enables:组使能信号
//      Address: 输出地址，10位宽
//中间变量：C:频率控制字，32位宽
//			        
//

module control(ClkIn10mhz, RegEnable, RegDataIn, Reset,
				 Enables, DLedout, Address, DutyCycle, AmOut, RAMwen, RAMren, Sel, rdaddress, wraddress);
	
	input ClkIn10mhz, RegEnable, Reset;
	input [63:0] RegDataIn;
	output [3:0]Enables, DLedout;
	output [9:0] Address, DutyCycle, rdaddress, wraddress;
	output [7:0] AmOut;
	output RAMwen, RAMren, Sel;
	
	
	reg [63:0]RegData;
	reg [9:0]rdaddress, wraddress;
	
	reg [31:0] C, FreScan;
										  								
		
	
	assign Enables = RegData[63:60];
	assign DLedout = ~RegData[63:60];
	assign Address[9:0] = C[31:22] + {RegData[17:10],2'b00};
	assign AmOut = RegData[25:18];
	assign DutyCycle = RegData[9:0];
	assign RAMwen = ~RegData[59];
	assign RAMren = RegData[59];
	assign Sel = RegData[59];
	//assign wraddress = Address;
	
	
	reg ClkFreScan;
	parameter p1 = 32'd10000;	//参数p1为分频的次数，改变这个参数来改变输出时钟ClkFreScan, ClkFreScan=10Mhz/p1.
	integer i1 = 1;
		
	
	always @ (posedge ClkIn10mhz)
	begin
		
		 if(!Reset)
			begin
				RegData[63:60] <= 4'b0001;//波形初始为正弦波
				RegData[59] <= 1'b0;//RAM初始为写
				RegData[58] <= 1'b1;
				RegData[57:26] <= 32'd429496;//频率初始为1khz  429496
				RegData[25:18] <= 8'b11111111;//幅值初始为最大
				RegData[17:10] <= 8'b00000000;//相位初始为0
				RegData[9:0] <= 10'b1000000000;//方波占空比初始为50%
				C <= 32'd0;//频率控制字初始为0
			end
					
		else 
			begin
				if(!RegEnable)		//取寄存器的值
					RegData <= RegDataIn;
				
				if(!RegData[59])	//输出实时波形
					begin
						wraddress <= Address; 	
						rdaddress <= 10'b0000000000; 	
					end
				else				//输出RAM中存储的波形
					begin
						rdaddress <= Address; 	
						wraddress <= 10'b0000000000;
					end	
			
				i1 <= i1 + 1;		//产生分频时钟
				if(i1 == (p1>>1))
				begin
					ClkFreScan <= ~ClkFreScan;
				end
				else if(i1 == p1)
				begin
					ClkFreScan <= ~ClkFreScan;
					i1 <= 1;
					
					if(RegData[58])
						begin
							FreScan <= FreScan + 32'd43;		//产生扫频量
						end
					else
						begin
							FreScan <= 32'd0;
						end
				end			
				
				//////////////////////////////////////
				C <= C + FreScan + RegData[57:26];		//累加器
				//////////////////////////////////////
			end
	end
	
	
endmodule