dds.v

来自「FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通」· Verilog 代码 · 共 54 行

//DDS.v	 	DDS总模块	2006-9-3	version:1.0		作者：田世坤
//输入：
//		
//		4294967296
//输出：

module DDS(ClkIn10mhz, Reset, RegEnable, ShiftClk, RegIn,
				  DLedout, DataOut, AmOut, U4dir_AmOut, U5dir_DataOut, U9dir_Shift);
	input ClkIn10mhz, Reset, RegEnable, ShiftClk, RegIn;
	output U4dir_AmOut, U5dir_DataOut, U9dir_Shift;
	output [3:0]DLedout;
	output [7:0]DataOut, AmOut;
	wire [3:0]DLedout;
	wire [7:0]DataOut, AmOut;
	
	wire [3:0]Enables;
	wire [63:0]ShiftReg;
	wire [9:0]Address, rdaddress, wraddress, DutyCycle;
	wire [7:0]DataSin, DataSquare, DataTriangle, DataRise, DataChOut, DataRAMOut;
	wire RAMwen, RAMren, Sel;
		
	assign U4dir_AmOut = 1'b1;
	assign U5dir_DataOut = 1'b1;
	assign U9dir_Shift = 1'b0;
				
LPM_SHIFTREa (ShiftClk, RegEnable, RegIn,
				ShiftReg);

control(ClkIn10mhz, RegEnable, ShiftReg, Reset,
		 Enables, DLedout, Address, DutyCycle, AmOut, RAMwen, RAMren, Sel, rdaddress, wraddress);

romlookup (Address, ClkIn10mhz,
			DataSin);
			
squwave(ClkIn10mhz, Address, DutyCycle,
				DataSquare);
				
triawave(ClkIn10mhz, Address, 
				DataTriangle);
				
risewave(ClkIn10mhz, Address,
				DataRise);
				
datachoose(Reset, DataSin, DataSquare, DataTriangle, DataRise, Enables, 
					DataChOut);

RAM (ClkIn10mhz, DataChOut, rdaddress, RAMren, wraddress, RAMwen,
	DataRAMOut);		//						

MUX (DataChOut, DataRAMOut, Sel, 
		DataOut);

endmodule