pulse_level_g_s.v

基于Verilog-HDL的硬件电路的实现 9.6 脉冲高电平和低电平持续时间的测量与显示 9.6.1 脉冲高电平和低电平持续时间测量的工作原理 9.6.2 高低电平持续时间测量模

module  PULSE_LEVEL_G_S  (PULSE, CLK, RST, PH, P, DP, LD, LED);
    input    PULSE;
    input    CLK, RST;
    output   PH;                   
    output   [3:0] DP;              
    output   [4:0] LD;              
    output   [3:0] P; 
    output   [7:0] LED;
    reg      [7:0] LED;
    wire     [16:0] H_LEVEL;
    wire     [7:0] L_LEVEL;
    wire     [3:0] BW, BQ, BB, BS, BG;

    PULSE_LEVEL_G  PULSE_LEVEL_G (CLK, PULSE, RST, H_LEVEL, L_LEVEL);   
    BIN_BCD   BIN_BCD   (CLK, H_LEVEL, BW, BQ, BB, BS, BG );	
    LCD  LCD  (CLK, RST, BW, BQ, BB, BS, BG, PH, P, DP, LD);

    always @ (posedge CLK)
       begin
            LED=L_LEVEL;
       end
endmodule


/**********  进行脉冲高低电平持续时间的测量 **********/	
module  PULSE_LEVEL_G  (CLK, CLKX, RST, H_LEVEL, L_LEVEL);   
    input    CLK, CLKX, RST;
    output   [16:0] H_LEVEL;
    output   [7:0]  L_LEVEL; 
    wire     CLKX_N;
    wire     [16:0] L_LEVEL_M;
       
    assign  CLKX_N=~CLKX;
    assign  L_LEVEL=L_LEVEL_M[7:0];

    HIGN_LEVEL  HIGN_LEVEL (CLK, CLKX, RST, H_LEVEL);
    HIGN_LEVEL  LOW_LEVEL (CLK, CLKX_N, RST, L_LEVEL_M);

endmodule

module  HIGN_LEVEL  (CLK, CLKX, RST, H_LEVEL);   
    input    CLK, CLKX, RST;
    output   [16:0] H_LEVEL;
    reg      [16:0] H_LEVEL;
 
    reg      [16:0] H_OUT; 
    reg      CNT_EN;
    wire     CNT_H_EN;
    wire     H_LOAD;
    wire     CNT_H_CLR;   

    always @ (posedge CLKX or negedge RST)
       begin
         if (!RST)
           begin
             CNT_EN=0;
           end
         else 
           begin
             CNT_EN=~CNT_EN;
           end
        end
    
    assign  CNT_H_EN=CLKX & CNT_EN;
    assign  H_LOAD=~CNT_H_EN;		
    assign  CNT_H_CLR=~(~CLKX & ~CNT_EN);   

    always @(posedge CLK or negedge CNT_H_CLR)
       begin
        if (!CNT_H_CLR)   
           H_OUT=0;
        else if (CNT_H_EN)
           begin
             if (H_OUT==99999)
                 H_OUT=99999;
             else 
                 H_OUT=H_OUT+1;
           end
       end
 
    always @ (posedge H_LOAD)
       begin
         H_LEVEL=H_OUT;
       end

endmodule


/*************数制转换**********************/					
module BIN_BCD (CLK, A, BW, BQ, BB, BS, BG);		
    input CLK;
    input  [16:0]A;        
    output [3:0]BW, BQ, BB, BS, BG;        	
    reg    [3:0]BW, BQ, BB, BS, BG;      
  					
    integer I;
    reg  [19:0]TEMP;
    reg  [16:0]C;
						
    					
    always @ (posedge CLK)
     begin
       C=A;
       TEMP=0;

       for (I=1; I<17; I=I+1)
           begin
           {TEMP, C}={TEMP[18:0], C, 1'b0};
           if (TEMP[3:0]>4'b0100)
              begin
                TEMP[3:0]=TEMP[3:0]+3;
              end 
           if (TEMP[7:4]>4'b0100)
              begin
                TEMP[7:4]=TEMP[7:4]+3;
              end 
           if (TEMP[11:8]>4'b0100)
              begin
                TEMP[11:8]=TEMP[11:8]+3;
              end 
           if (TEMP[15:12]>4'b0100)
              begin
                TEMP[15:12]=TEMP[15:12]+3;
              end 
           if (TEMP[19:16]>4'b0100)
              begin
                TEMP[19:16]=TEMP[19:16]+3;
              end 
           {BW, BQ, BB,  BS, BG}={TEMP[18:0], A[0]};
           end
     end
  
endmodule


/******************LCD显示**********************/
module  LCD (CLK, CLR, NUMW, NUMQ, NUMB, NUMS, NUMG, PH, P, DP, LD);
    input    CLK, CLR;
    input    [3:0] NUMW, NUMQ, NUMB, NUMS, NUMG;
    output   PH;
    output   [3:0] DP;
    output   [4:0] LD;
    output   [3:0] P;
    reg      [4:0] LD;
    reg      [3:0] P;
    reg      [2:0]COUNT;

    assign  PH=CLK;
    assign  DP[3]=CLK; 
    assign  DP[2]=CLK; 
    assign  DP[1]=CLK; 
    assign  DP[0]=CLK; 
                 
  
    always @ (posedge CLK or negedge CLR)
         if (!CLR)
            COUNT<=0;
         else if (COUNT==5)
            COUNT<=1;
         else 
            COUNT<=COUNT+1;
    
    
    always @ (COUNT)
      begin
         case (COUNT)
           3'b001:begin
                     P=NUMW;
                     LD=5'b00001;
                  end
           3'b010:begin
                     P=NUMQ;
                     LD=5'b00010;
                  end
           3'b011:begin
                     P=NUMB;
                     LD=5'b00100;
                  end
           3'b100:begin
                     P=NUMS;
                     LD=5'b01000;
                  end
           3'b101:begin
                     P=NUMG;
                     LD=5'b10000;
                  end
        endcase           
     end
endmodule