pulse_level.v

来自「基于Verilog-HDL的硬件电路的实现 9.6 脉冲高电平和低电平持续时」· Verilog 代码 · 共 76 行

module  PULSE_LEVEL  (CLK, CLKX, RST, H_LEVEL, L_LEVEL);   
    input    CLK, CLKX, RST;
    output   [16:0] H_LEVEL;
    output   [7:0]  L_LEVEL; 
    reg      [16:0] H_LEVEL;
    reg      [7:0]  L_LEVEL;  
 
    reg      [16:0] H_OUT; 
    reg      [7:0]  L_OUT; 
    reg      CNT_EN;
    wire     CNT_H_EN, CNT_L_EN;
    wire     H_LOAD, L_LOAD;
    wire     CNT_H_CLR, CNT_L_CLR;
             


    always @ (posedge CLKX or negedge RST)
       begin
         if (!RST)
           begin
             CNT_EN=0;
           end
         else 
           begin
             CNT_EN=~CNT_EN;
           end
        end
    
    assign  CNT_H_EN=CLKX & CNT_EN;
    assign  CNT_L_EN=~CLKX & CNT_EN;
    assign  H_LOAD=~CNT_H_EN;
    assign  L_LOAD=~CNT_L_EN;				
    assign  CNT_H_CLR=~(~CLKX & ~CNT_EN);          
    assign  CNT_L_CLR=~(CLKX & CNT_EN);

    always @(posedge CLK or negedge CNT_H_CLR)
       begin
        if (!CNT_H_CLR)   
           H_OUT=0;
        else if (CNT_H_EN)
           begin
             if (H_OUT==99999)
                 H_OUT=99999;
             else 
                 H_OUT=H_OUT+1;
           end
       end

    always @(posedge CLK or negedge CNT_L_CLR)
       begin
        if (!CNT_L_CLR)   
           L_OUT=0;
        else if (CNT_L_EN)
           begin
             if (L_OUT==255)
                 L_OUT=255;
             else 
                 L_OUT=L_OUT+1;
           end
       end

    always @ (posedge H_LOAD)
       begin
         H_LEVEL=H_OUT;
       end

    always @ (posedge L_LOAD)
       begin
         L_LEVEL=L_OUT;
       end
endmodule