pulse_level_g.v

来自「基于Verilog-HDL的硬件电路的实现 9.6 脉冲高电平和低电平持续时」· Verilog 代码 · 共 65 行

module  PULSE_LEVEL_G  (CLK, CLKX, RST, H_LEVEL, L_LEVEL);   
    input    CLK, CLKX, RST;
    output   [16:0] H_LEVEL;
    output   [7:0]  L_LEVEL; 
    wire     CLKX_N;
    wire     [16:0] L_LEVEL_M;
       
    assign  CLKX_N=~CLKX;
    assign  L_LEVEL=L_LEVEL_M[7:0];

    HIGN_LEVEL  HIGN_LEVEL (CLK, CLKX, RST, H_LEVEL);
    HIGN_LEVEL  LOW_LEVEL  (CLK, CLKX_N, RST, L_LEVEL_M);

endmodule

module  HIGN_LEVEL  (CLK, CLKX, RST, H_LEVEL);   
    input    CLK, CLKX, RST;
    output   [16:0] H_LEVEL;
    reg      [16:0] H_LEVEL;
    reg      [16:0] H_OUT; 
    reg      CNT_EN;
    wire     CNT_H_EN;
    wire     H_LOAD;
    wire     CNT_H_CLR;   

    always @ (posedge CLKX or negedge RST)
       begin
         if (!RST)
           begin
             CNT_EN=0;
           end
         else 
           begin
             CNT_EN=~CNT_EN;
           end
        end
    
    assign  CNT_H_EN=CLKX & CNT_EN;
    assign  H_LOAD=~CNT_H_EN;		
    assign  CNT_H_CLR=~(~CLKX & ~CNT_EN);   

    always @(posedge CLK or negedge CNT_H_CLR)
       begin
        if (!CNT_H_CLR)   
           H_OUT=0;
        else if (CNT_H_EN)
           begin
             if (H_OUT==99999)
                 H_OUT=99999;
             else 
                 H_OUT=H_OUT+1;
           end
       end
 
    always @ (posedge H_LOAD)
       begin
         H_LEVEL=H_OUT;
       end

endmodule