fsm_temp.ncf

Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。

TIMESPEC TS01 = FROM:PADS:TO:FFS:50.000000;
TIMESPEC TS02 = FROM:FFS:TO:FFS:50.000000;
TIMESPEC TS03 = FROM:FFS:TO:PADS:50.000000;
TIMESPEC TS04 = FROM:PADS:TO:PADS:50.000000;