news5f.cr.mti

Verilog HDL语言编写的5分频电路。采用两路时钟相逻辑作用产生。

E:/assignment/Verilog/task/test/news5f/news5f.v {1 {vlog -work work E:/assignment/Verilog/task/test/news5f/news5f.v
Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
-- Compiling module S5F32

Top level modules:
	S5F32

} {} {}} E:/assignment/Verilog/task/test/news5f/tb_news5f.v {1 {vlog -work work E:/assignment/Verilog/task/test/news5f/tb_news5f.v
Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
-- Compiling module tb_S5F

Top level modules:
	tb_S5F

} {} {}} E:/assignment/Verilog/task/test/news5f/news5f_top.v {1 {vlog -work work E:/assignment/Verilog/task/test/news5f/news5f_top.v
Model Technology ModelSim SE vlog 6.0 Compiler 2004.08 Aug 19 2004
-- Compiling module s5f

Top level modules:
	s5f

} {} {}}