📄 m74148a.tan.rpt
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Timing Analyzer report for m74148a
Tue Mar 28 09:14:39 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 9.436 ns ; i3 ; gs ; ; ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F484C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; Off ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+---------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+----+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+----+
; N/A ; None ; 9.436 ns ; i3 ; eo ;
; N/A ; None ; 9.436 ns ; i3 ; gs ;
; N/A ; None ; 9.316 ns ; i0 ; eo ;
; N/A ; None ; 9.316 ns ; i0 ; gs ;
; N/A ; None ; 9.257 ns ; i5 ; eo ;
; N/A ; None ; 9.256 ns ; i5 ; gs ;
; N/A ; None ; 9.246 ns ; i2 ; eo ;
; N/A ; None ; 9.246 ns ; i2 ; gs ;
; N/A ; None ; 9.150 ns ; i4 ; eo ;
; N/A ; None ; 9.149 ns ; i4 ; gs ;
; N/A ; None ; 9.138 ns ; i3 ; a1 ;
; N/A ; None ; 9.097 ns ; i6 ; eo ;
; N/A ; None ; 9.096 ns ; i6 ; gs ;
; N/A ; None ; 9.090 ns ; i6 ; a2 ;
; N/A ; None ; 9.032 ns ; i1 ; eo ;
; N/A ; None ; 9.032 ns ; i1 ; gs ;
; N/A ; None ; 9.022 ns ; i2 ; a1 ;
; N/A ; None ; 8.980 ns ; i7 ; eo ;
; N/A ; None ; 8.979 ns ; i7 ; gs ;
; N/A ; None ; 8.973 ns ; i7 ; a2 ;
; N/A ; None ; 8.897 ns ; i6 ; a0 ;
; N/A ; None ; 8.856 ns ; ei ; a2 ;
; N/A ; None ; 8.844 ns ; i5 ; a1 ;
; N/A ; None ; 8.819 ns ; i5 ; a0 ;
; N/A ; None ; 8.737 ns ; i4 ; a1 ;
; N/A ; None ; 8.736 ns ; i4 ; a2 ;
; N/A ; None ; 8.728 ns ; i3 ; a0 ;
; N/A ; None ; 8.706 ns ; i4 ; a0 ;
; N/A ; None ; 8.684 ns ; i6 ; a1 ;
; N/A ; None ; 8.675 ns ; ei ; eo ;
; N/A ; None ; 8.675 ns ; ei ; gs ;
; N/A ; None ; 8.650 ns ; i5 ; a2 ;
; N/A ; None ; 8.567 ns ; i7 ; a1 ;
; N/A ; None ; 8.537 ns ; i2 ; a0 ;
; N/A ; None ; 8.432 ns ; i7 ; a0 ;
; N/A ; None ; 8.321 ns ; i1 ; a0 ;
; N/A ; None ; 8.261 ns ; ei ; a1 ;
; N/A ; None ; 8.252 ns ; ei ; a0 ;
+-------+-------------------+-----------------+------+----+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Tue Mar 28 09:14:38 2006
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off m74148a -c m74148a --timing_analysis_only
Info: Longest tpd from source pin "i3" to destination pin "eo" is 9.436 ns
Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_F2; Fanout = 3; PIN Node = 'i3'
Info: 2: + IC(3.681 ns) + CELL(0.280 ns) = 5.195 ns; Loc. = LC_X52_Y22_N3; Fanout = 2; COMB Node = 'reduce_nor~40'
Info: 3: + IC(0.334 ns) + CELL(0.366 ns) = 5.895 ns; Loc. = LC_X52_Y22_N6; Fanout = 1; COMB Node = 'eo~13'
Info: 4: + IC(1.165 ns) + CELL(2.376 ns) = 9.436 ns; Loc. = PIN_H2; Fanout = 0; PIN Node = 'eo'
Info: Total cell delay = 4.256 ns ( 45.10 % )
Info: Total interconnect delay = 5.180 ns ( 54.90 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings
Info: Processing ended: Tue Mar 28 09:14:39 2006
Info: Elapsed time: 00:00:01
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