m74148a.map.summary

来自「采用verilog设计」· SUMMARY 代码 · 共 14 行

Flow Status : Successful - Tue Mar 28 09:14:21 2006
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : m74148a
Top-level Entity Name : m74148a
Family : Stratix
Met timing requirements : N/A
Total logic elements : 11
Total pins : 14
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0