m74148a.map.eqn

采用verilog设计

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--A1L32 is reduce_or~50
--operation mode is normal

A1L32 = i5 & i4;


--A1L42 is reduce_or~51
--operation mode is normal

A1L42 = i7 & i6;


--A1L52 is reduce_or~52
--operation mode is normal

A1L52 = i3 & i2;


--A1L6 is a1~3
--operation mode is normal

A1L6 = ei # A1L42 & (A1L52 # !A1L32);


--A1L2 is a0~146
--operation mode is normal

A1L2 = i5 & i3 & (i1 # !i2);


--A1L3 is a0~147
--operation mode is normal

A1L3 = i5 & !i4 # !i6;


--A1L4 is a0~148
--operation mode is normal

A1L4 = ei # i7 & (A1L2 # A1L3);


--A1L22 is reduce_nor~40
--operation mode is normal

A1L22 = !i0 # !i1 # !i2 # !i3;


--A1L31 is gs~6
--operation mode is normal

A1L31 = ei # A1L32 & A1L42 & !A1L22;


--A1L11 is eo~13
--operation mode is normal

A1L11 = ei # A1L22 # !A1L42 # !A1L32;


--A1L8 is a2~16
--operation mode is normal

A1L8 = ei # i5 & i4 & A1L42;


--ei is ei
--operation mode is input

ei = INPUT();


--i5 is i5
--operation mode is input

i5 = INPUT();


--i4 is i4
--operation mode is input

i4 = INPUT();


--i7 is i7
--operation mode is input

i7 = INPUT();


--i6 is i6
--operation mode is input

i6 = INPUT();


--i3 is i3
--operation mode is input

i3 = INPUT();


--i2 is i2
--operation mode is input

i2 = INPUT();


--i1 is i1
--operation mode is input

i1 = INPUT();


--i0 is i0
--operation mode is input

i0 = INPUT();


--a2 is a2
--operation mode is output

a2 = OUTPUT(A1L8);


--a1 is a1
--operation mode is output

a1 = OUTPUT(A1L6);


--a0 is a0
--operation mode is output

a0 = OUTPUT(A1L4);


--gs is gs
--operation mode is output

gs = OUTPUT(A1L31);


--eo is eo
--operation mode is output

eo = OUTPUT(A1L11);