cpu_test.v

一个支持精简指令的16位的risc cpu

`include "ram.v"
`include "cpu.v"

`timescale 10ns/1ns
//`define clk_cycle 100
module cpu_test;
	reg	reset,clock;
	//integer test;
	//reg	[(4*16):0]	mnemonic;
	reg	[15:0]		PC_addr,IR_addr;
	wire	[15:0]		data_out;
	wire	[15:0]		ram_out;
	wire	[15:0]		addr;
	wire	read,write,halt;

//cpu和ram连接部分

cpu t_cpu(.clk(clock),.rst(reset),.halt(halt),.read(read),.write(write),.addr(addr),.data_out(data_out),.data_in(ram_out));

ram t_ram(.read(read),.write(write),.addr(addr),.data_in(data_out),.data_out(ram_out));

initial
begin
 #0   reset=0;
      clock=0;
      $readmemb("Fibonacci.txt",t_ram.memory);
      $display("ram loaded successfully!");
      $strobe("%t   %h    %h",$time,t_ram.memory[16'h0002],t_ram.memory[16'h0001]);
      //$strobe("%t       %d",$time,t_ram.memory[16'h0002]);
    
    
    #70 reset=1;
	#100 reset = 0;
    $timeformat(-9,1,"ns",12);
   // $stop;
    
end


always #50 clock=~clock;

endmodule