mux_a.v

来自「一个支持精简指令的16位的risc cpu」· Verilog 代码 · 共 17 行

//`timescale 10ns/1ns
module mux_a(data_in3,i2,b_bus,lors);
output	[15:0]	b_bus;
input	[15:0]	data_in3;
input	[4:0]	i2;
input	lors;


assign	b_bus = (lors)? {{11{i2[4]}},i2} : data_in3;

endmodule