counter.v

来自「一个支持精简指令的16位的risc cpu」· Verilog 代码 · 共 44 行

//`timescale 10ns/1ns
module counter(pc_addr,to_d1,base_addr,bias_addr,op_j,op_jr,load_pc,reset);
output	[15:0]	pc_addr,to_d1;
input	[15:0]	base_addr;
input	[7:0]	bias_addr;
input	load_pc,reset,op_j,op_jr;
reg	[15:0]	pc_addr,to_d1;

always @ (posedge reset or posedge load_pc)
	begin
		if(reset)
			begin
			pc_addr <= 16'b0000_0000_0000_0000;
			to_d1 <= 16'b0000_0000_0000_0000;
			end
		else	if(load_pc)
			begin
			if(op_j&&(~op_jr))
				begin
				pc_addr <= pc_addr + {{8{bias_addr[7]}},bias_addr};
				to_d1 <= pc_addr + 1;
				end			
			else	if(op_jr&&(~op_j))
				begin
				pc_addr <= base_addr + {{8{bias_addr[7]}},bias_addr};
				to_d1 <= pc_addr + 1;
				end
			else	if(op_j&&op_jr)
				begin
				pc_addr <= pc_addr + {{8{bias_addr[7]}},bias_addr};
				to_d1 <= 16'bzzzz_zzzz_zzzz_zzzz;
				end
			else
				begin
				pc_addr <= pc_addr + 1;
				to_d1 <= 16'bzzzz_zzzz_zzzz_zzzz;
				end
			end
	end

endmodule