group_reg.v

一个支持精简指令的16位的risc cpu

module group_reg(clk1,d1_ena,load_gpr,r_r,w_r,reset,d1,d2,d3,data_in,data_out1or2,data_out3);
output	[15:0]	data_out1or2,data_out3;
input	[15:0] data_in;
input	[2:0]	d1,d2,d3;
input	reset,clk1,d1_ena,load_gpr,r_r,w_r;

wire	[15:0] data_out1or2,data_out3;
wire	r_d1,r_d2,r_d3,w;

assign r_d1=load_gpr && r_r && d1_ena;
assign r_d2=load_gpr && r_r && (~d1_ena);
assign r_d3=load_gpr && r_r && (~d1_ena);
assign w=load_gpr && w_r;

reg1 m_reg1(.clk1(clk1),.reset(reset),.d1(d1),.d2(d2),.r_d1(r_d1),.r_d2(r_d2),.w(w),.data_in(data_in),
		.m0(data_out1or2),.m1(data_out1or2),.m2(data_out1or2),.m3(data_out1or2),
		.m4(data_out1or2),.m5(data_out1or2),.m6(data_out1or2),.m7(data_out1or2));
reg2 m_reg2(.clk1(clk1),.reset(reset),.d1(d1),.d3(d3),.r_d3(r_d3),.w(w),.data_in(data_in),
		.m0(data_out3),.m1(data_out3),.m2(data_out3),.m3(data_out3),
		.m4(data_out3),.m5(data_out3),.m6(data_out3),.m7(data_out3));
endmodule

module reg1(clk1,reset,d1,d2,r_d1,r_d2,w,data_in,m0,m1,m2,m3,m4,m5,m6,m7);
output	[15:0] m0,m1,m2,m3,m4,m5,m6,m7;
input	[15:0] data_in;
input	[2:0]	d1,d2;
input	clk1,reset,r_d1,r_d2,w;

reg	[15:0]	r0,r1,r2,r3,r4,r5,r6,r7;
reg	[15:0] m0,m1,m2,m3,m4,m5,m6,m7;

always @ (posedge clk1)
begin
if(reset)
	begin
	r0<=0;r1<=0;r2<=0;r3<=0;r4<=0;r5<=0;r6<=0;r7<=0;
	m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz;
	end
else if(w)
	begin
	case(d1)
		3'b000:r0<=r0;
		3'b001:r1<=data_in;
		3'b010:r2<=data_in; 	
		3'b011:r3<=data_in;  				
		3'b100:r4<=data_in; 	
		3'b101:r5<=data_in;  	
		3'b110:r6<=data_in;  	
		3'b111:r7<=data_in;
	endcase
	end
else if(r_d1)
	begin
		case(d1)
			3'b000:begin m0<=0;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
			3'b001:begin m0<=16'hzzzz;m1<=r1;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
			3'b010:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=r2;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end	
			3'b011:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=r3;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end				
			3'b100:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=r4;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end	
			3'b101:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=r5;m6<=16'hzzzz;m7<=16'hzzzz; end	
			3'b110:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=r6;m7<=16'hzzzz; end	
			3'b111:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=r7; end
		endcase
	end
else if(r_d2)
	begin
		case(d2)
			3'b000:begin m0<=0;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
			3'b001:begin m0<=16'hzzzz;m1<=r1;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
			3'b010:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=r2;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end	
			3'b011:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=r3;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end				
			3'b100:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=r4;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end	
			3'b101:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=r5;m6<=16'hzzzz;m7<=16'hzzzz; end	
			3'b110:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=r6;m7<=16'hzzzz; end	
			3'b111:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=r7; end
		endcase
	end
end
endmodule

module reg2(clk1,reset,d1,d3,r_d3,w,data_in,m0,m1,m2,m3,m4,m5,m6,m7);
output	[15:0] m0,m1,m2,m3,m4,m5,m6,m7;
input	[15:0] data_in;
input	[2:0]	d1,d3;
input	clk1,reset,r_d3,w;

reg	[15:0]	r0,r1,r2,r3,r4,r5,r6,r7;
reg	[15:0] m0,m1,m2,m3,m4,m5,m6,m7;

always @ (posedge clk1)
begin
if(reset)
	begin
	r0<=0;r1<=0;r2<=0;r3<=0;r4<=0;r5<=0;r6<=0;r7<=0;
	m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz;
	end
else if(w)
	begin
	case(d1)
		3'b000:r0<=r0;
		3'b001:r1<=data_in;
		3'b010:r2<=data_in; 	
		3'b011:r3<=data_in;  				
		3'b100:r4<=data_in; 	
		3'b101:r5<=data_in;  	
		3'b110:r6<=data_in;  	
		3'b111:r7<=data_in;
	endcase
	end
else if(r_d3)
	begin
		case(d3)
			3'b000:begin m0<=0;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
			3'b001:begin m0<=16'hzzzz;m1<=r1;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end
			3'b010:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=r2;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end	
			3'b011:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=r3;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end				
			3'b100:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=r4;m5<=16'hzzzz;m6<=16'hzzzz;m7<=16'hzzzz; end	
			3'b101:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=r5;m6<=16'hzzzz;m7<=16'hzzzz; end	
			3'b110:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=r6;m7<=16'hzzzz; end	
			3'b111:begin m0<=16'hzzzz;m1<=16'hzzzz;m2<=16'hzzzz;m3<=16'hzzzz;m4<=16'hzzzz;m5<=16'hzzzz;m6<=16'hzzzz;m7<=r7; end
		endcase
	end
end
endmodule