cpu.v

一个支持精简指令的16位的risc cpu

`timescale 10ns/1ns
`include "alu.v"
`include "clk1.v"
`include "group_reg.v"
`include "counter.v"
`include "machine.v"
`include "mux_a.v"
`include "mux_r.v"
`include "register.v"
`include "addreg.v"


module cpu(clk,rst,data_in,data_out,read,write,addr,halt);
output	[15:0]	data_out;
output	[15:0]	addr;
output	read,write,halt;
input	[15:0]data_in;
input	rst,clk;

//clk1
wire	clk1;

//machine
wire	read,write,halt,r_r,w_r,d1_ena,load_ir,load_pc,load_gpr,load_alu,load_pa,mux_p1,mux_p2,mux_a,mux_pa;
wire	[1:0]	mux_r;
wire	[2:0]	alu_c;

//ram
//wire	[15:0]	data_out;

//register
wire	[15:0]	opc_iraddrs;

//com_reg
wire	[15:0]	data_out,data_out3;

//alu
wire	[15:0] C3_BUS;

//addreg
wire	[15:0]	addr;

//counter
wire	[15:0]	pc_addr,to_d1;

//mux_a
wire	[15:0]	b_bus;

//mux_r
wire	[15:0]	mux_out;

clk1 m_clk1(.clk(clk),.clk1(clk1));

machine m_machine(	.reset(rst),.clk(clk),.d1_in(data_out),.opcode(opc_iraddrs[15:11]),
			.r(read),.w(write),.h(halt),.r_r(r_r),.w_r(w_r),.d1_ena(d1_ena),
			.load_ir(load_ir),.load_pc(load_pc),.load_gpr(load_gpr),.load_alu(load_alu),.load_pa(load_pa),
			.mux_p1(mux_p1),.mux_p2(mux_p2),.mux_a(mux_a),.mux_pa(mux_pa),.mux_r(mux_r),.alu_c(alu_c));

register m_register(.clk1(clk1),.ena(load_ir),.data(data_in),.opc_iraddrs(opc_iraddrs));

group_reg  m_group_reg(.reset(rst),.d1(opc_iraddrs[10:8]),.d2(opc_iraddrs[7:5]),.d3(opc_iraddrs[4:2]),.load_gpr(load_gpr),
			.r_r(r_r),.w_r(w_r),.d1_ena(d1_ena),.clk1(clk1),.data_in(mux_out),.data_out1or2(data_out),.data_out3(data_out3));

alu m_alu(.A_BUS(data_out),.B_BUS(b_bus),.ALU_OPCODE(alu_c),.CP(clk1),.WORK_EX(load_alu),.C3_BUS(C3_BUS));

addreg m_addreg(.clk1(clk1),.pc_addr(pc_addr),.alu_out(C3_BUS),.reset(rst),.load_pa(load_pa),.mux_pa(mux_pa),.addr(addr));

counter m_counter(.reset(rst),.load_pc(load_pc),.op_j(mux_p1),.op_jr(mux_p2),.base_addr(data_out),.bias_addr(opc_iraddrs[7:0]),.pc_addr(pc_addr),.to_d1(to_d1));

mux_a m_mux_a(.data_in3(data_out3),.i2(opc_iraddrs[4:0]),.lors(mux_a),.b_bus(b_bus));

mux_r m_mux_r(.mux_r(mux_r),.mux_out(mux_out),.i1(opc_iraddrs[7:0]),.alu_out(C3_BUS),.from_mem(data_in),.from_pc(to_d1));


endmodule