addreg.v

一个支持精简指令的16位的risc cpu

module addreg(clk1,addr,reset,load_pa,mux_pa,pc_addr,alu_out);
output	[15:0]	addr;
input	[15:0]	pc_addr,alu_out;
input	reset,load_pa,mux_pa,clk1;
reg	[15:0]	addr;

always @ (clk1)
begin
	if(reset)
		addr <= 16'h0000;
	else if(load_pa)
		begin
			if(mux_pa)
				addr <= alu_out;
			else if(~mux_pa)
				addr <= pc_addr;
		end
end
		
endmodule