machine.v

一个支持精简指令的16位的risc cpu

//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {machine}}
module machine (clk, opcode, d1_in, reset, r, w, h, r_r, w_r, d1_ena, load_ir, load_pc, load_gpr, load_alu, load_pa, mux_p1, mux_p2, mux_a, mux_pa, mux_r, alu_c);

input clk;
input [4:0] opcode;
input [15:0] d1_in;
input reset;
output r;
output w;
output h;
output r_r;
output w_r;
output d1_ena;
output load_ir;
output load_pc;
output load_gpr;
output load_alu;
output load_pa;
output mux_p1;
output mux_p2;
output mux_a;
output mux_pa;
output [1:0] mux_r;
output [2:0] alu_c;

//}} End of automatically maintained section

// -- Enter your statements here -- // 
reg r,w,h,w_r,r_r,d1_ena;
       reg load_ir,load_pc,load_gpr,load_alu,load_pa,mux_p1,mux_p2,mux_a,mux_pa;
       reg [1:0] mux_r;
       reg [2:0] alu_c;
       reg [2:0] state;
       

       parameter  L   =5'b00000, 
                  S   =5'b00001,
                  LI  =5'b00010,
                  ADD =5'b00011,
                  SUB =5'b00100,
                  NOT =5'b00101,
                  AND =5'b00110,
                  OR  =5'b00111,
                  LSH =5'b01000,
                  RSH =5'b01001,
                  RSHU=5'b01010,
                  J   =5'b01011,
                  JR  =5'b01100,
                  BZ  =5'b01101,
                  BNZ =5'b01110,
                  H   =5'b01111;

       always@(posedge clk)
             
             begin
                   if(reset)
                      begin
                            state <=3'b000;
                            {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
                            {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                            {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                            mux_r <=2'b00;
                            alu_c <=3'b000;
                      end
                    else
                         clk_cycle;
                    end

//----------------------begin of task clk_cycle---------------------------
                    task clk_cycle;
                         begin 
                               casex(state)
3'b000:
        begin
              {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b10000;
              {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
              {r,w,h,w_r,r_r,d1_ena} <=6'b100000;
              mux_r <=2'b00;
              alu_c <=3'b000;
              state <=3'b001;
        end

3'b001:
        begin
		if(opcode==H)
		   begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b001000;
                      mux_r <=2'b00;
                      alu_c <=3'b000;   
                 end
		else
             	 if(opcode==L||opcode==S)                    
                 begin
                 {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
                 {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0010;
                 {r,w,h,w_r,r_r,d1_ena} <=6'b000010;
                 mux_r <=2'b00;
                 alu_c <=3'b000;//
                end
              else 
                   if(opcode==LI)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;//change
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000100;
                      mux_r <=2'b10;
                      alu_c <=3'b000;   
                      end
              else 
                   if(opcode==ADD||opcode==SUB||opcode==AND||opcode==OR||opcode==NOT)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000010;
                      mux_r <=2'b00;//change
                      alu_c <=3'b000;   
                      end
              else
                   if(opcode==LSH||opcode==RSH||opcode==RSHU)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000010;
                      mux_r <=2'b00;
                      alu_c <=3'b000;   
                      end
              else 
                   if(opcode==JR||opcode==BZ||opcode==BNZ)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000011;
                      mux_r <=2'b00;
                      alu_c <=3'b000;   
                      end
              else

                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b000;   
                      end
              state <=3'b010;
        end

3'b010:
        begin
              if(opcode==L||opcode==S)//
                 begin
                 {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                 {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0010;
                 {r,w,h,w_r,r_r,d1_ena} <=6'b000000;//
                 mux_r <=2'b00;
                 alu_c <=3'b011;
                 end 
              else
		     if(opcode==ADD)////
			 begin
                 		{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                 		{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                 		{r,w,h,w_r,r_r,d1_ena} <=6'b000000;//
                		 mux_r <=2'b00;
                 		 alu_c <=3'b011;
                 	end 
		else
                   if(opcode==SUB)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b111;   
                      end
              else 
                   if(opcode==NOT)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b100;   
                      end
              else
                   if(opcode==AND)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b101;   
                      end
              else
                   if(opcode==OR)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b110;   
                      end
              else
                   if(opcode==LSH)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b000;   
                      end
              else
                   if(opcode==RSH)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;