risc_cpu.v

一个支持精简指令的16位的risc cpu

//******************cpu.v*****************
module cpu(clk,rst,data_in,data_out,read,write,addr,halt);
output	[15:0]	data_out;
output	[15:0]	addr;
output	read,write,halt;
input	[15:0]data_in;
input	rst,clk;

//clk1
wire	clk1;

//machine
wire	read,write,halt,r_r,w_r,d1_ena,load_ir,load_pc,load_gpr,load_alu,load_pa,mux_p1,mux_p2,mux_a,mux_pa;
wire	[1:0]	mux_r;
wire	[2:0]	alu_c;

//ram
//wire	[15:0]	data_out;

//register
wire	[15:0]	opc_iraddrs;

//com_reg
wire	[15:0]	data_out,data_out3;

//alu
wire	[15:0] C3_BUS;

//addreg
wire	[15:0]	addr;

//counter
wire	[15:0]	pc_addr,to_d1;

//mux_a
wire	[15:0]	b_bus;

//mux_r
wire	[15:0]	mux_out;

clk1 m_clk1(.clk(clk),.clk1(clk1));

machine m_machine(	.reset(rst),.clk(clk),.d1_in(data_out),.opcode(opc_iraddrs[15:11]),
			.r(read),.w(write),.h(halt),.r_r(r_r),.w_r(w_r),.d1_ena(d1_ena),
			.load_ir(load_ir),.load_pc(load_pc),.load_gpr(load_gpr),.load_alu(load_alu),.load_pa(load_pa),
			.mux_p1(mux_p1),.mux_p2(mux_p2),.mux_a(mux_a),.mux_pa(mux_pa),.mux_r(mux_r),.alu_c(alu_c));

register m_register(.clk1(clk1),.ena(load_ir),.data(data_in),.opc_iraddrs(opc_iraddrs));

group_reg  m_group_reg(.reset(rst),.d1(opc_iraddrs[10:8]),.d2(opc_iraddrs[7:5]),.d3(opc_iraddrs[4:2]),.load_gpr(load_gpr),
			.r_r(r_r),.w_r(w_r),.d1_ena(d1_ena),.clk1(clk1),.data_in(mux_out),.data_out1or2(data_out),.data_out3(data_out3));

alu m_alu(.A_BUS(data_out),.B_BUS(b_bus),.ALU_OPCODE(alu_c),.CP(clk1),.WORK_EX(load_alu),.C3_BUS(C3_BUS));

addreg m_addreg(.clk1(clk1),.pc_addr(pc_addr),.alu_out(C3_BUS),.reset(rst),.load_pa(load_pa),.mux_pa(mux_pa),.addr(addr));

counter m_counter(.reset(rst),.load_pc(load_pc),.op_j(mux_p1),.op_jr(mux_p2),.base_addr(data_out),.bias_addr(opc_iraddrs[7:0]),.pc_addr(pc_addr),.to_d1(to_d1));

mux_a m_mux_a(.data_in3(data_out3),.i2(opc_iraddrs[4:0]),.lors(mux_a),.b_bus(b_bus));

mux_r m_mux_r(.mux_r(mux_r),.mux_out(mux_out),.i1(opc_iraddrs[7:0]),.alu_out(C3_BUS),.from_mem(data_in),.from_pc(to_d1));


endmodule
//*****************************machine.v***************
//{{ Section below this comment is automatically maintained
//   and may be overwritten
//{module {machine}}
module machine (clk, opcode, d1_in, reset, r, w, h, r_r, w_r, d1_ena, load_ir, load_pc, load_gpr, load_alu, load_pa, mux_p1, mux_p2, mux_a, mux_pa, mux_r, alu_c);

input clk;
input [4:0] opcode;
input [15:0] d1_in;
input reset;
output r;
output w;
output h;
output r_r;
output w_r;
output d1_ena;
output load_ir;
output load_pc;
output load_gpr;
output load_alu;
output load_pa;
output mux_p1;
output mux_p2;
output mux_a;
output mux_pa;
output [1:0] mux_r;
output [2:0] alu_c;

//}} End of automatically maintained section

// -- Enter your statements here -- // 
reg r,w,h,w_r,r_r,d1_ena;
       reg load_ir,load_pc,load_gpr,load_alu,load_pa,mux_p1,mux_p2,mux_a,mux_pa;
       reg [1:0] mux_r;
       reg [2:0] alu_c;
       reg [2:0] state;
       

       parameter  L   =5'b00000, 
                  S   =5'b00001,
                  LI  =5'b00010,
                  ADD =5'b00011,
                  SUB =5'b00100,
                  NOT =5'b00101,
                  AND =5'b00110,
                  OR  =5'b00111,
                  LSH =5'b01000,
                  RSH =5'b01001,
                  RSHU=5'b01010,
                  J   =5'b01011,
                  JR  =5'b01100,
                  BZ  =5'b01101,
                  BNZ =5'b01110,
                  H   =5'b01111;

       always@(posedge clk)
             
             begin
                   if(reset)
                      begin
                            state <=3'b000;
                            {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
                            {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                            {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                            mux_r <=2'b00;
                            alu_c <=3'b000;
                      end
                    else
                         clk_cycle;
                    end

//----------------------begin of task clk_cycle---------------------------
                    task clk_cycle;
                         begin 
                               casex(state)
3'b000:
        begin
              {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b10000;
              {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
              {r,w,h,w_r,r_r,d1_ena} <=6'b100000;
              mux_r <=2'b00;
              alu_c <=3'b000;
              state <=3'b001;
        end

3'b001:
        begin
		if(opcode==H)
		   begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b001000;
                      mux_r <=2'b00;
                      alu_c <=3'b000;   
                 end
		else
             	 if(opcode==L||opcode==S)                    
                 begin
                 {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
                 {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0010;
                 {r,w,h,w_r,r_r,d1_ena} <=6'b000010;
                 mux_r <=2'b00;
                 alu_c <=3'b000;//
                end
              else 
                   if(opcode==LI)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;//change
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000100;
                      mux_r <=2'b10;
                      alu_c <=3'b000;   
                      end
              else 
                   if(opcode==ADD||opcode==SUB||opcode==AND||opcode==OR||opcode==NOT)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000010;
                      mux_r <=2'b00;//change
                      alu_c <=3'b000;   
                      end
              else
                   if(opcode==LSH||opcode==RSH||opcode==RSHU)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000010;
                      mux_r <=2'b00;
                      alu_c <=3'b000;   
                      end
              else 
                   if(opcode==JR||opcode==BZ||opcode==BNZ)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00100;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000011;
                      mux_r <=2'b00;
                      alu_c <=3'b000;   
                      end
              else

                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00000;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b000;   
                      end
              state <=3'b010;
        end

3'b010:
        begin
              if(opcode==L||opcode==S)//
                 begin
                 {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                 {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0010;
                 {r,w,h,w_r,r_r,d1_ena} <=6'b000000;//
                 mux_r <=2'b00;
                 alu_c <=3'b011;
                 end 
              else
		     if(opcode==ADD)////
			 begin
                 		{load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                 		{mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                 		{r,w,h,w_r,r_r,d1_ena} <=6'b000000;//
                		 mux_r <=2'b00;
                 		 alu_c <=3'b011;
                 	end 
		else
                   if(opcode==SUB)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b111;   
                      end
              else 
                   if(opcode==NOT)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b100;   
                      end
              else
                   if(opcode==AND)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b101;   
                      end
              else
                   if(opcode==OR)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b110;   
                      end
              else
                   if(opcode==LSH)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b000;   
                      end
              else
                   if(opcode==RSH)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0000;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b001;   
                      end
              else
                   if(opcode==RSHU)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b00010;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0010;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000000;
                      mux_r <=2'b00;
                      alu_c <=3'b010;   
                      end
              else
                   if(opcode==JR)
                      begin
                      {load_ir,load_pc,load_gpr,load_alu,load_pa} <=5'b01100;
                      {mux_p1,mux_p2,mux_a,mux_pa} <=4'b0100;
                      {r,w,h,w_r,r_r,d1_ena} <=6'b000100;
                      mux_r <=2'b11;
                      alu_c <=3'b000;   
                      end
		else
			if(opcode==J)
                      begin