qep_data_bus.tan.qmsg

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

{ "Info" "ITDB_TSU_RESULT" "cnt_pulse:t_cnt_pulse_0\|cnt_out_reg\[6\] clr1_in clk_input 14.300 ns register " "Info: tsu for register \"cnt_pulse:t_cnt_pulse_0\|cnt_out_reg\[6\]\" (data pin = \"clr1_in\", clock pin = \"clk_input\") is 14.300 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.700 ns + Longest pin register " "Info: + Longest pin to register delay is 15.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.800 ns) 3.800 ns clr1_in 1 PIN PIN_67 367 " "Info: 1: + IC(0.000 ns) + CELL(3.800 ns) = 3.800 ns; Loc. = PIN_67; Fanout = 367; PIN Node = 'clr1_in'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "" { clr1_in } "NODE_NAME" } "" } } { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 32 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(6.300 ns) + CELL(1.300 ns) 11.400 ns rtl~51 2 COMB LC1_A36 8 " "Info: 2: + IC(6.300 ns) + CELL(1.300 ns) = 11.400 ns; Loc. = LC1_A36; Fanout = 8; COMB Node = 'rtl~51'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "7.600 ns" { clr1_in rtl~51 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(1.300 ns) 15.700 ns cnt_pulse:t_cnt_pulse_0\|cnt_out_reg\[6\] 3 REG LC4_A8 1 " "Info: 3: + IC(3.000 ns) + CELL(1.300 ns) = 15.700 ns; Loc. = LC4_A8; Fanout = 1; REG Node = 'cnt_pulse:t_cnt_pulse_0\|cnt_out_reg\[6\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "4.300 ns" { rtl~51 cnt_pulse:t_cnt_pulse_0|cnt_out_reg[6] } "NODE_NAME" } "" } } { "cnt_pulse.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.400 ns 40.76 % " "Info: Total cell delay = 6.400 ns ( 40.76 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.300 ns 59.24 % " "Info: Total interconnect delay = 9.300 ns ( 59.24 % )" {  } {  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "15.700 ns" { clr1_in rtl~51 cnt_pulse:t_cnt_pulse_0|cnt_out_reg[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "15.700 ns" { clr1_in clr1_in~out rtl~51 cnt_pulse:t_cnt_pulse_0|cnt_out_reg[6] } { 0.000ns 0.000ns 6.300ns 3.000ns } { 0.000ns 3.800ns 1.300ns 1.300ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.900 ns + " "Info: + Micro setup delay of destination is 0.900 ns" {  } { { "cnt_pulse.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 5 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_input destination 2.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_input\" to destination register is 2.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns clk_input 1 CLK PIN_55 492 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_55; Fanout = 492; CLK Node = 'clk_input'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "" { clk_input } "NODE_NAME" } "" } } { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 2.300 ns cnt_pulse:t_cnt_pulse_0\|cnt_out_reg\[6\] 2 REG LC4_A8 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 2.300 ns; Loc. = LC4_A8; Fanout = 1; REG Node = 'cnt_pulse:t_cnt_pulse_0\|cnt_out_reg\[6\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "1.400 ns" { clk_input cnt_pulse:t_cnt_pulse_0|cnt_out_reg[6] } "NODE_NAME" } "" } } { "cnt_pulse.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/cnt_pulse.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns 39.13 % " "Info: Total cell delay = 0.900 ns ( 39.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 60.87 % " "Info: Total interconnect delay = 1.400 ns ( 60.87 % )" {  } {  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input cnt_pulse:t_cnt_pulse_0|cnt_out_reg[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out cnt_pulse:t_cnt_pulse_0|cnt_out_reg[6] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.900ns 0.000ns } } }  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "15.700 ns" { clr1_in rtl~51 cnt_pulse:t_cnt_pulse_0|cnt_out_reg[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "15.700 ns" { clr1_in clr1_in~out rtl~51 cnt_pulse:t_cnt_pulse_0|cnt_out_reg[6] } { 0.000ns 0.000ns 6.300ns 3.000ns } { 0.000ns 3.800ns 1.300ns 1.300ns } } } { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input cnt_pulse:t_cnt_pulse_0|cnt_out_reg[6] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out cnt_pulse:t_cnt_pulse_0|cnt_out_reg[6] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.900ns 0.000ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "ale_in data_inout\[1\] data_bus:t_data_bus\|add_reg\[1\] 29.500 ns register " "Info: tco from clock \"ale_in\" to destination pin \"data_inout\[1\]\" through register \"data_bus:t_data_bus\|add_reg\[1\]\" is 29.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ale_in source 8.000 ns + Longest register " "Info: + Longest clock path from clock \"ale_in\" to source register is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.800 ns) 3.800 ns ale_in 1 CLK PIN_8 6 " "Info: 1: + IC(0.000 ns) + CELL(3.800 ns) = 3.800 ns; Loc. = PIN_8; Fanout = 6; CLK Node = 'ale_in'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "" { ale_in } "NODE_NAME" } "" } } { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.200 ns) + CELL(0.000 ns) 8.000 ns data_bus:t_data_bus\|add_reg\[1\] 2 REG LC5_F36 13 " "Info: 2: + IC(4.200 ns) + CELL(0.000 ns) = 8.000 ns; Loc. = LC5_F36; Fanout = 13; REG Node = 'data_bus:t_data_bus\|add_reg\[1\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "4.200 ns" { ale_in data_bus:t_data_bus|add_reg[1] } "NODE_NAME" } "" } } { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 47.50 % " "Info: Total cell delay = 3.800 ns ( 47.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.200 ns 52.50 % " "Info: Total interconnect delay = 4.200 ns ( 52.50 % )" {  } {  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "8.000 ns" { ale_in data_bus:t_data_bus|add_reg[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { ale_in ale_in~out data_bus:t_data_bus|add_reg[1] } { 0.000ns 0.000ns 4.200ns } { 0.000ns 3.800ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns + " "Info: + Micro clock to output delay of source is 0.400 ns" {  } { { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 15 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "21.100 ns + Longest register pin " "Info: + Longest register to pin delay is 21.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_bus:t_data_bus\|add_reg\[1\] 1 REG LC5_F36 13 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_F36; Fanout = 13; REG Node = 'data_bus:t_data_bus\|add_reg\[1\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "" { data_bus:t_data_bus|add_reg[1] } "NODE_NAME" } "" } } { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.400 ns) 4.100 ns data_bus:t_data_bus\|Decoder~53 2 COMB LC2_F20 9 " "Info: 2: + IC(2.700 ns) + CELL(1.400 ns) = 4.100 ns; Loc. = LC2_F20; Fanout = 9; COMB Node = 'data_bus:t_data_bus\|Decoder~53'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "4.100 ns" { data_bus:t_data_bus|add_reg[1] data_bus:t_data_bus|Decoder~53 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(0.700 ns) 7.500 ns cnt_pulse:t_cnt_pulse_4\|cnt_out\[1\]~91 3 COMB LC1_E34 1 " "Info: 3: + IC(2.700 ns) + CELL(0.700 ns) = 7.500 ns; Loc. = LC1_E34; Fanout = 1; COMB Node = 'cnt_pulse:t_cnt_pulse_4