qep_data_bus.tan.qmsg

来自「基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "ale_in " "Info: Assuming node \"ale_in\" is an undefined clock" {  } { { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 18 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ale_in" } } } }  } 0}  } {  } 0}