qep_data_bus.tan.qmsg

基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL的

{ "Info" "ITDB_FULL_SLACK_RESULT" "clk_input register qep4:t_qep4_2\|prestate\[0\] register qep4:t_qep4_2\|lpm_counter:qep_reg_rtl_9\|alt_counter_f10ke:wysi_counter\|q\[15\] 11.1 ns " "Info: Slack time is 11.1 ns for clock \"clk_input\" between source register \"qep4:t_qep4_2\|prestate\[0\]\" and destination register \"qep4:t_qep4_2\|lpm_counter:qep_reg_rtl_9\|alt_counter_f10ke:wysi_counter\|q\[15\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "71.94 MHz 13.9 ns " "Info: Fmax is 71.94 MHz (period= 13.9 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "23.700 ns + Largest register register " "Info: + Largest register to register requirement is 23.700 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "25.000 ns + " "Info: + Setup relationship between source and destination is 25.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 25.000 ns " "Info: + Latch edge is 25.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk_input 25.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk_input\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk_input 25.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk_input\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_input destination 2.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_input\" to destination register is 2.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns clk_input 1 CLK PIN_55 492 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_55; Fanout = 492; CLK Node = 'clk_input'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "" { clk_input } "NODE_NAME" } "" } } { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 2.300 ns qep4:t_qep4_2\|lpm_counter:qep_reg_rtl_9\|alt_counter_f10ke:wysi_counter\|q\[15\] 2 REG LC8_E4 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 2.300 ns; Loc. = LC8_E4; Fanout = 3; REG Node = 'qep4:t_qep4_2\|lpm_counter:qep_reg_rtl_9\|alt_counter_f10ke:wysi_counter\|q\[15\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "1.400 ns" { clk_input qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns 39.13 % " "Info: Total cell delay = 0.900 ns ( 39.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 60.87 % " "Info: Total interconnect delay = 1.400 ns ( 60.87 % )" {  } {  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_input source 2.300 ns - Longest register " "Info: - Longest clock path from clock \"clk_input\" to source register is 2.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns clk_input 1 CLK PIN_55 492 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_55; Fanout = 492; CLK Node = 'clk_input'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "" { clk_input } "NODE_NAME" } "" } } { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 2.300 ns qep4:t_qep4_2\|prestate\[0\] 2 REG LC2_E5 46 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 2.300 ns; Loc. = LC2_E5; Fanout = 46; REG Node = 'qep4:t_qep4_2\|prestate\[0\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "1.400 ns" { clk_input qep4:t_qep4_2|prestate[0] } "NODE_NAME" } "" } } { "qep4.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 9 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns 39.13 % " "Info: Total cell delay = 0.900 ns ( 39.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 60.87 % " "Info: Total interconnect delay = 1.400 ns ( 60.87 % )" {  } {  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input qep4:t_qep4_2|prestate[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out qep4:t_qep4_2|prestate[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.900ns 0.000ns } } }  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.900ns 0.000ns } } } { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input qep4:t_qep4_2|prestate[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out qep4:t_qep4_2|prestate[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns - " "Info: - Micro clock to output delay of source is 0.400 ns" {  } { { "qep4.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 9 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.900 ns - " "Info: - Micro setup delay of destination is 0.900 ns" {  } { { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.900ns 0.000ns } } } { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input qep4:t_qep4_2|prestate[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out qep4:t_qep4_2|prestate[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.900ns 0.000ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.600 ns - Longest register register " "Info: - Longest register to register delay is 12.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns qep4:t_qep4_2\|prestate\[0\] 1 REG LC2_E5 46 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_E5; Fanout = 46; REG Node = 'qep4:t_qep4_2\|prestate\[0\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "" { qep4:t_qep4_2|prestate[0] } "NODE_NAME" } "" } } { "qep4.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep4.v" 9 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.800 ns) 2.200 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\] 2 COMB LC2_E1 2 " "Info: 2: + IC(1.400 ns) + CELL(0.800 ns) = 2.200 ns; Loc. = LC2_E1; Fanout = 2; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[1\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.200 ns" { qep4:t_qep4_2|prestate[0] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[1] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.400 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\] 3 COMB LC3_E1 2 " "Info: 3: + IC(0.000 ns) + CELL(0.200 ns) = 2.400 ns; Loc. = LC3_E1; Fanout = 2; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[2\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.200 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[1] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[2] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.600 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\] 4 COMB LC4_E1 2 " "Info: 4: + IC(0.000 ns) + CELL(0.200 ns) = 2.600 ns; Loc. = LC4_E1; Fanout = 2; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[3\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.200 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[2] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[3] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 2.800 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\] 5 COMB LC5_E1 2 " "Info: 5: + IC(0.000 ns) + CELL(0.200 ns) = 2.800 ns; Loc. = LC5_E1; Fanout = 2; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[4\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.200 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[3] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[4] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.000 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\] 6 COMB LC6_E1 2 " "Info: 6: + IC(0.000 ns) + CELL(0.200 ns) = 3.000 ns; Loc. = LC6_E1; Fanout = 2; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[5\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.200 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[4] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[5] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.200 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\] 7 COMB LC7_E1 2 " "Info: 7: + IC(0.000 ns) + CELL(0.200 ns) = 3.200 ns; Loc. = LC7_E1; Fanout = 2; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[6\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.200 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[5] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[6] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 3.400 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\] 8 COMB LC8_E1 2 " "Info: 8: + IC(0.000 ns) + CELL(0.200 ns) = 3.400 ns; Loc. = LC8_E1; Fanout = 2; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[7\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.200 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[6] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[7] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(0.200 ns) 3.900 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\] 9 COMB LC1_E3 2 " "Info: 9: + IC(0.300 ns) + CELL(0.200 ns) = 3.900 ns; Loc. = LC1_E3; Fanout = 2; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[8\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.500 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[7] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[8] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.100 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\] 10 COMB LC2_E3 2 " "Info: 10: + IC(0.000 ns) + CELL(0.200 ns) = 4.100 ns; Loc. = LC2_E3; Fanout = 2; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[9\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.200 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[8] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[9] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.300 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\] 11 COMB LC3_E3 2 " "Info: 11: + IC(0.000 ns) + CELL(0.200 ns) = 4.300 ns; Loc. = LC3_E3; Fanout = 2; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[10\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.200 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[9] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[10] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.500 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\] 12 COMB LC4_E3 2 " "Info: 12: + IC(0.000 ns) + CELL(0.200 ns) = 4.500 ns; Loc. = LC4_E3; Fanout = 2; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[11\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.200 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[10] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[11] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.700 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\] 13 COMB LC5_E3 2 " "Info: 13: + IC(0.000 ns) + CELL(0.200 ns) = 4.700 ns; Loc. = LC5_E3; Fanout = 2; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[12\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.200 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[11] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[12] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 4.900 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\] 14 COMB LC6_E3 2 " "Info: 14: + IC(0.000 ns) + CELL(0.200 ns) = 4.900 ns; Loc. = LC6_E3; Fanout = 2; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[13\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.200 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[12] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[13] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 5.100 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\] 15 COMB LC7_E3 1 " "Info: 15: + IC(0.000 ns) + CELL(0.200 ns) = 5.100 ns; Loc. = LC7_E3; Fanout = 1; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|a_csnbuffer:result_node\|cout\[14\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.200 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[13] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[14] } "NODE_NAME" } "" } } { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 18 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 6.300 ns qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|unreg_res_node\[15\] 16 COMB LC8_E3 1 " "Info: 16: + IC(0.000 ns) + CELL(1.200 ns) = 6.300 ns; Loc. = LC8_E3; Fanout = 1; COMB Node = 'qep4:t_qep4_2\|lpm_add_sub:add_rtl_15\|addcore:adder\|unreg_res_node\[15\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "1.200 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[14] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|unreg_res_node[15] } "NODE_NAME" } "" } } { "addcore.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/addcore.tdf" 95 16 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.300 ns) 9.700 ns qep4:t_qep4_2\|lpm_counter:qep_reg_rtl_9\|alt_counter_f10ke:wysi_counter\|data_path\[15\] 17 COMB LC1_C3 1 " "Info: 17: + IC(2.100 ns) + CELL(1.300 ns) = 9.700 ns; Loc. = LC1_C3; Fanout = 1; COMB Node = 'qep4:t_qep4_2\|lpm_counter:qep_reg_rtl_9\|alt_counter_f10ke:wysi_counter\|data_path\[15\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "3.400 ns" { qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|unreg_res_node[15] qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|data_path[15] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 285 12 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(0.700 ns) 12.600 ns qep4:t_qep4_2\|lpm_counter:qep_reg_rtl_9\|alt_counter_f10ke:wysi_counter\|q\[15\] 18 REG LC8_E4 3 " "Info: 18: + IC(2.200 ns) + CELL(0.700 ns) = 12.600 ns; Loc. = LC8_E4; Fanout = 3; REG Node = 'qep4:t_qep4_2\|lpm_counter:qep_reg_rtl_9\|alt_counter_f10ke:wysi_counter\|q\[15\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.900 ns" { qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|data_path[15] qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } "" } } { "alt_counter_f10ke.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/alt_counter_f10ke.tdf" 271 2 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.600 ns 52.38 % " "Info: Total cell delay = 6.600 ns ( 52.38 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.000 ns 47.62 % " "Info: Total interconnect delay = 6.000 ns ( 47.62 % )" {  } {  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "12.600 ns" { qep4:t_qep4_2|prestate[0] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[1] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[2] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[3] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[4] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[5] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[6] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[7] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[8] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[9] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[10] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[11] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[12] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[13] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[14] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|unreg_res_node[15] qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|data_path[15] qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.600 ns" { qep4:t_qep4_2|prestate[0] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[1] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[2] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[3] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[4] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[5] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[6] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[7] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[8] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[9] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[10] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[11] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[12] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[13] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[14] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|unreg_res_node[15] qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|data_path[15] qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } { 0.000ns 1.400ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.300ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.100ns 2.200ns } { 0.000ns 0.800ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.200ns 1.300ns 0.700ns } } }  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.900ns 0.000ns } } } { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input qep4:t_qep4_2|prestate[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out qep4:t_qep4_2|prestate[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.900ns 0.000ns } } } { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "12.600 ns" { qep4:t_qep4_2|prestate[0] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[1] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[2] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[3] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[4] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[5] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[6] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[7] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[8] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[9] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[10] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[11] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[12] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[13] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[14] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|unreg_res_node[15] qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|data_path[15] qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.600 ns" { qep4:t_qep4_2|prestate[0] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[1] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[2] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[3] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[4] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[5] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[6] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[7] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[8] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[9] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[10] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[11] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[12] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[13] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|a_csnbuffer:result_node|cout[14] qep4:t_qep4_2|lpm_add_sub:add_rtl_15|addcore:adder|unreg_res_node[15] qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|data_path[15] qep4:t_qep4_2|lpm_counter:qep_reg_rtl_9|alt_counter_f10ke:wysi_counter|q[15] } { 0.000ns 1.400ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.300ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 2.100ns 2.200ns } { 0.000ns 0.800ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 0.200ns 1.200ns 1.300ns 0.700ns } } }  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "ale_in " "Info: No valid register-to-register data paths exist for clock \"ale_in\"" {  } {  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk_input register data_bus:t_data_bus\|write_reg\[1\] register data_bus:t_data_bus\|link_cs_wr 100 ps " "Info: Minimum slack time is 100 ps for clock \"clk_input\" between source register \"data_bus:t_data_bus\|write_reg\[1\]\" and destination register \"data_bus:t_data_bus\|link_cs_wr\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.800 ns + Shortest register register " "Info: + Shortest register to register delay is 0.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns data_bus:t_data_bus\|write_reg\[1\] 1 REG LC3_F33 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_F33; Fanout = 3; REG Node = 'data_bus:t_data_bus\|write_reg\[1\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "" { data_bus:t_data_bus|write_reg[1] } "NODE_NAME" } "" } } { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 24 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.100 ns) + CELL(0.700 ns) 0.800 ns data_bus:t_data_bus\|link_cs_wr 2 REG LC5_F33 112 " "Info: 2: + IC(0.100 ns) + CELL(0.700 ns) = 0.800 ns; Loc. = LC5_F33; Fanout = 112; REG Node = 'data_bus:t_data_bus\|link_cs_wr'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.800 ns" { data_bus:t_data_bus|write_reg[1] data_bus:t_data_bus|link_cs_wr } "NODE_NAME" } "" } } { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 30 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.700 ns 87.50 % " "Info: Total cell delay = 0.700 ns ( 87.50 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.100 ns 12.50 % " "Info: Total interconnect delay = 0.100 ns ( 12.50 % )" {  } {  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.800 ns" { data_bus:t_data_bus|write_reg[1] data_bus:t_data_bus|link_cs_wr } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.800 ns" { data_bus:t_data_bus|write_reg[1] data_bus:t_data_bus|link_cs_wr } { 0.0ns 0.1ns } { 0.0ns 0.7ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.700 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.700 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk_input 25.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk_input\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk_input 25.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk_input\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_input destination 2.300 ns + Longest register " "Info: + Longest clock path from clock \"clk_input\" to destination register is 2.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns clk_input 1 CLK PIN_55 492 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_55; Fanout = 492; CLK Node = 'clk_input'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "" { clk_input } "NODE_NAME" } "" } } { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 2.300 ns data_bus:t_data_bus\|link_cs_wr 2 REG LC5_F33 112 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 2.300 ns; Loc. = LC5_F33; Fanout = 112; REG Node = 'data_bus:t_data_bus\|link_cs_wr'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "1.400 ns" { clk_input data_bus:t_data_bus|link_cs_wr } "NODE_NAME" } "" } } { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 30 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns 39.13 % " "Info: Total cell delay = 0.900 ns ( 39.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 60.87 % " "Info: Total interconnect delay = 1.400 ns ( 60.87 % )" {  } {  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input data_bus:t_data_bus|link_cs_wr } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out data_bus:t_data_bus|link_cs_wr } { 0.0ns 0.0ns 1.4ns } { 0.0ns 0.9ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_input source 2.300 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_input\" to source register is 2.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.900 ns) 0.900 ns clk_input 1 CLK PIN_55 492 " "Info: 1: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = PIN_55; Fanout = 492; CLK Node = 'clk_input'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "" { clk_input } "NODE_NAME" } "" } } { "qep_data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/qep_data_bus.v" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 2.300 ns data_bus:t_data_bus\|write_reg\[1\] 2 REG LC3_F33 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 2.300 ns; Loc. = LC3_F33; Fanout = 3; REG Node = 'data_bus:t_data_bus\|write_reg\[1\]'" {  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "1.400 ns" { clk_input data_bus:t_data_bus|write_reg[1] } "NODE_NAME" } "" } } { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 24 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns 39.13 % " "Info: Total cell delay = 0.900 ns ( 39.13 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns 60.87 % " "Info: Total interconnect delay = 1.400 ns ( 60.87 % )" {  } {  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input data_bus:t_data_bus|write_reg[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out data_bus:t_data_bus|write_reg[1] } { 0.0ns 0.0ns 1.4ns } { 0.0ns 0.9ns 0.0ns } } }  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input data_bus:t_data_bus|link_cs_wr } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out data_bus:t_data_bus|link_cs_wr } { 0.0ns 0.0ns 1.4ns } { 0.0ns 0.9ns 0.0ns } } } { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input data_bus:t_data_bus|write_reg[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out data_bus:t_data_bus|write_reg[1] } { 0.0ns 0.0ns 1.4ns } { 0.0ns 0.9ns 0.0ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.400 ns - " "Info: - Micro clock to output delay of source is 0.400 ns" {  } { { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 24 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.100 ns + " "Info: + Micro hold delay of destination is 1.100 ns" {  } { { "data_bus.v" "" { Text "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/data_bus.v" 30 -1 0 } }  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input data_bus:t_data_bus|link_cs_wr } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out data_bus:t_data_bus|link_cs_wr } { 0.0ns 0.0ns 1.4ns } { 0.0ns 0.9ns 0.0ns } } } { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input data_bus:t_data_bus|write_reg[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out data_bus:t_data_bus|write_reg[1] } { 0.0ns 0.0ns 1.4ns } { 0.0ns 0.9ns 0.0ns } } }  } 0}  } { { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "0.800 ns" { data_bus:t_data_bus|write_reg[1] data_bus:t_data_bus|link_cs_wr } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "0.800 ns" { data_bus:t_data_bus|write_reg[1] data_bus:t_data_bus|link_cs_wr } { 0.0ns 0.1ns } { 0.0ns 0.7ns } } } { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input data_bus:t_data_bus|link_cs_wr } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out data_bus:t_data_bus|link_cs_wr } { 0.0ns 0.0ns 1.4ns } { 0.0ns 0.9ns 0.0ns } } } { "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" "" { Report "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus_cmp.qrpt" Compiler "qep_data_bus" "UNKNOWN" "V1" "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/db/qep_data_bus.quartus_db" { Floorplan "E:/Cpld_Work_File/Verilog_Pro/qep_data_bus/" "" "2.300 ns" { clk_input data_bus:t_data_bus|write_reg[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "2.300 ns" { clk_input clk_input~out data_bus:t_data_bus|write_reg[1] } { 0.0ns 0.0ns 1.4ns } { 0.0ns 0.9ns 0.0ns } } }  } 0}