qep_data_bus.tan.qmsg

来自「基于地址总线接口的四倍频编码器信号接口的 FPGA实现 Verilog HDL」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 15 21:16:59 2005 " "Info: Processing started: Thu Dec 15 21:16:59 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off qep_data_bus -c qep_data_bus " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off qep_data_bus -c qep_data_bus" {  } {  } 0}