fifo3_inst.vhd

使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真

fifo3_inst : fifo3 PORT MAP(
		data	 => data_sig,
		wrreq	 => wrreq_sig,
		rdreq	 => rdreq_sig,
		clock	 => clock_sig,
		aclr	 => aclr_sig,
		q	 => q_sig,
		full	 => full_sig
	);