p_2_s.v

来自「这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下」· Verilog 代码 · 共 31 行

module p_2_s(seria_out,clk,rst,cnt,data_in);
output  seria_out;
input   clk,rst;
input [7:0] data_in;
input [2:0] cnt;

reg   [7:0] databuf;
reg         seria_buf;

assign seria_out=seria_buf;

always@(data_in)
 databuf<=data_in; 
    
always@(posedge clk or negedge rst )
   if(!rst)  seria_buf<=0;
   else 
     begin
         case(cnt)
           3'b000: seria_buf<=databuf[7];
           3'b001: seria_buf<=databuf[6];
           3'b010: seria_buf<=databuf[5];
           3'b011: seria_buf<=databuf[4];
           3'b100: seria_buf<=databuf[3];
           3'b101: seria_buf<=databuf[2];
           3'b110: seria_buf<=databuf[1];
           3'b111: seria_buf<=databuf[0];
           default:seria_buf<=0;
          endcase
      end
endmodule