demux.v

这是PCM电话传输系统模型的verilog程序,是一个modlesim开发环境下的工程文件,并有波形仿真结果.

module demux(rst,clk,clk1,flag,cnt,data_in,data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7,
             data_out8,data_out9,data_out10,data_out11,data_out12,data_out13,data_out14,data_out15,
             data_out16,data_out17,data_out18,data_out19,data_out20,data_out21,data_out22,data_out23,
             data_out24,data_out25,data_out26,data_out27,data_out28,data_out29,data_out30,data_out31); 
input rst,clk,clk1,flag;     //clk1=8*488
input [7:0]  data_in;
input [4:0]  cnt;
output[7:0]  data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7,
             data_out8,data_out9,data_out10,data_out11,data_out12,data_out13,data_out14,data_out15,
             data_out16,data_out17,data_out18,data_out19,data_out20,data_out21,data_out22,data_out23,
             data_out24,data_out25,data_out26,data_out27,data_out28,data_out29,data_out30,data_out31;

reg [7:0]    data_out0,data_out1,data_out2,data_out3,data_out4,data_out5,data_out6,data_out7,
             data_out8,data_out9,data_out10,data_out11,data_out12,data_out13,data_out14,data_out15,
             data_out16,data_out17,data_out18,data_out19,data_out20,data_out21,data_out22,data_out23,
             data_out24,data_out25,data_out26,data_out27,data_out28,data_out29,data_out30,data_out31;
reg [7:0]    dabuf; 
    
always@(negedge clk or negedge rst)
  if(!rst) begin
           dabuf<=0;
           end   
  else     dabuf<=data_in;
 
 
  always begin:ab
    @(negedge clk)
     if (!clk1) disable ab;
     else 
       @(negedge clk)
         if(!flag) disable ab;
         else
         @(negedge clk)
          case(cnt)
          5'b0_0001:  data_out0<=dabuf;
          5'b0_0010:  data_out1<=dabuf;
          5'b0_0011:  data_out2<=dabuf;
          5'b0_0100:  data_out3<=dabuf;     
          5'b0_0101:  data_out4<=dabuf;
          5'b0_0110:  data_out5<=dabuf;
          5'b0_0111:  data_out6<=dabuf;
          5'b0_1000:  data_out7<=dabuf;     
          5'b0_1001:  data_out8<=dabuf;
          5'b0_1010:  data_out9<=dabuf;
          5'b0_1011:  data_out10<=dabuf;
          5'b0_1100:  data_out11<=dabuf;     
          5'b0_1101:  data_out12<=dabuf;
          5'b0_1110:  data_out13<=dabuf;
          5'b0_1111:  data_out14<=dabuf;
          5'b1_0000:  data_out15<=dabuf;
          5'b1_0001:  data_out16<=dabuf;
          5'b1_0010:  data_out17<=dabuf;
          5'b1_0011:  data_out18<=dabuf;
          5'b1_0100:  data_out19<=dabuf;    
          5'b1_0101:  data_out20<=dabuf;
          5'b1_0110:  data_out21<=dabuf;
          5'b1_0111:  data_out22<=dabuf;
          5'b1_1000:  data_out23<=dabuf;    
          5'b1_1001:  data_out24<=dabuf;
          5'b1_1010:  data_out25<=dabuf;
          5'b1_1011:  data_out26<=dabuf;
          5'b1_1100:  data_out27<=dabuf;    
          5'b1_1101:  data_out28<=dabuf;
          5'b1_1110:  data_out29<=dabuf;
          5'b1_1111:  data_out30<=dabuf;
          5'b0_0000:  data_out31<=dabuf;
     endcase	
    end 
endmodule